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1. 发明授权

US06335495B1 Patterning a layered chrome-copper structure disposed on a dielectric substrate 失效
标题翻译：对设置在电介质基板上的分层铬铜结构进行成形
公开(公告)号：US06335495B1
公开(公告)日：2002-01-01
申请号：US09343073
申请日：1999-06-29
申请人： Donald S. Farquhar , Edmond O. Fey , Elizabeth F. Foster , Michael J. Klodowski
发明人： Donald S. Farquhar , Edmond O. Fey , Elizabeth F. Foster , Michael J. Klodowski
IPC分类号： H01K111
CPC分类号： H05K3/4641 , H05K1/0224 , H05K3/064 , H05K3/388 , H05K2201/015 , H05K2201/0338
摘要： An electrical structure, comprising a first dielectric layer, a patterned layer on the first dielectric layer, and a second dielectric layer on the patterned layer. The patterned layer includes a metal pattern on the first dielectric layer, a metallic pattern on the metal pattern, and a plugged pattern within a remaining space of the patterned layer. The plugged pattern includes a dielectric material. The second dielectric layer is adhesively bonded to a top surface of the patterned layer. The second dielectric layer includes the dielectric material.
摘要翻译：电结构，包括第一电介质层，第一电介质层上的图案化层和图案化层上的第二电介质层。图案化层包括在第一介电层上的金属图案，金属图案上的金属图案，以及图案化层的剩余空间内的堵塞图案。堵塞图案包括电介质材料。第二电介质层粘合到图案化层的顶表面上。第二电介质层包括电介质材料。

2. 发明授权

US06843929B1 Accelerated etching of chromium 失效
标题翻译：加速蚀刻铬
公开(公告)号：US06843929B1
公开(公告)日：2005-01-18
申请号：US09514526
申请日：2000-02-28
申请人： Donald S. Farquhar , Edmond O. Fey , Elizabeth Foster , Michael J. Klodowski , Paul G. Rickerl
发明人： Donald S. Farquhar , Edmond O. Fey , Elizabeth Foster , Michael J. Klodowski , Paul G. Rickerl
IPC分类号： C23F1/26 , H01L21/3213 , B44C1/22
CPC分类号： H01L21/32134 , C23F1/26
摘要： A method and associated structure for increasing the rate at which a chromium volume is etched when the chromium body is contacted by an acid solution such as hydrochloric acid. The etch rate is increased by a metallic or steel body in continuous electrical contact with the chromium volume, both of which are in continuous contact with the acid solution. At a temperature between about 21° C. and about 52° C., and a hydrochloric acid concentration (molarity) between about 1.2 M and about 2.4 M, the etch rate is at least a factor of about two greater than an etch rate that would occur in an absence of the steel body. In one embodiment, the chromium volume is a chromium layer that rests upon a conductive layer that includes a metal such as copper, wherein the acid solution is not in contact with the conductive layer. In another embodiment, the chromium volume is a chromium layer located under a conductive layer that includes a metal such as copper, wherein the steel body and the acid solution both contact the chromium layer through an opening in the conductive layer such that the opening exposes the chromium layer.
摘要翻译：一种用于提高当铬体与诸如盐酸的酸溶液接触时铬体积被蚀刻的速率的方法和相关结构。蚀刻速率由与铬体积连续电接触的金属或钢体增加，两者都与酸溶液连续接触。在约21℃至约52℃的温度和约1.2M至约2.4M之间的盐酸浓度（摩尔浓度）之间，蚀刻速率至少比蚀刻速率大约两倍，将在没有钢体的情况下发生。在一个实施方案中，铬体积是沉积在包括诸如铜的金属的导电层上的铬层，其中酸溶液不与导电层接触。在另一个实施方案中，铬体积是位于导电层下方的铬层，该层包括诸如铜的金属，其中钢体和酸溶液都通过导电层中的开口接触铬层，使得开口暴露于铬层。

3. 发明授权

US06395998B1 Electronic package having an adhesive retaining cavity 有权
标题翻译：具有粘合剂保持腔的电子封装
公开(公告)号：US06395998B1
公开(公告)日：2002-05-28
申请号：US09661652
申请日：2000-09-13
申请人： Donald S. Farquhar , Gregory A. Kevern , Michael J. Klodowski
发明人： Donald S. Farquhar , Gregory A. Kevern , Michael J. Klodowski
IPC分类号： H05K116
CPC分类号： H01L23/145 , H01L23/13 , H01L2924/0002 , Y10T29/4913 , H01L2924/00
摘要： An electronic package and method of making the electronic package is provided. An opening in a thermally conductive member of the electronic package is formed to substantially prevent adhesive which can bleed from under a substrate mounted and secured on the thermally conductive member from contacting a portion of the thermally conductive member upon which an electrical element will be mounted.
摘要翻译：提供电子封装和制造电子封装的方法。形成电子封装件的导热构件中的开口，以基本上防止粘合剂，该粘合剂可以从安装和固定在导热构件上的基板下方泄漏，以接触将要安装电气元件的导热构件的一部分。

4. 发明授权

US07059049B2 Electronic package with optimized lamination process 失效
标题翻译：电子封装具有优化的层压工艺
公开(公告)号：US07059049B2
公开(公告)日：2006-06-13
申请号：US10253725
申请日：2002-09-24
申请人： Donald S. Farquhar , James D. Herard , Michael J. Klodowski , David Questad , Der-jin Woan
发明人： Donald S. Farquhar , James D. Herard , Michael J. Klodowski , David Questad , Der-jin Woan
IPC分类号： H01K3/10
CPC分类号： H05K3/4641 , H01L21/4853 , H01L21/4857 , H01L23/3735 , H01L23/49822 , H01L23/49894 , H01L24/16 , H01L2224/13099 , H01L2224/16225 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01068 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/15311 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/351 , H05K1/0271 , H05K1/114 , H05K3/429 , H05K3/4602 , H05K3/4608 , H05K3/4623 , H05K3/4626 , H05K3/4632 , H05K3/4688 , H05K2201/0141 , H05K2201/015 , H05K2201/0191 , H05K2201/0209 , H05K2201/068 , H05K2201/09509 , H05K2201/09536 , H05K2201/09554 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , H05K2203/061 , H05K2203/068 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49163 , Y10T29/49165 , H01L2924/00
摘要： An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T1MIN and a maximum temperature T1MAX. T1MAX constrains the ductility of the first dielectric layer to be at least D1 following the laminating. T1MAX depends on D1 and on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T2MIN and a maximum temperature T2MAX. T2MAX constrains the ductility of the second dielectric layer to be at least D2 following the laminating. T2MAX depends on D2 and on a second dielectric material comprised by the second dielectric layer.
摘要翻译：电子封装和形成方法。提供具有第一和第二相对表面的导热层。第一电介质层在加压下被层压在导热层的第一相对表面上，温度在最低温度T 1 1MIN和最高温度T 1MAX之间。在层压之后，T 1MAX 3将第一介电层的延展性约束至少为D 1。 T 1MAX取决于D 1和在由第一介电层组成的第一电介质材料上。在加压下将第二电介质层在导热层的第二相对表面上，在最低温度T 2 M 2 N 2和最大温度T 2 MAX之间的温度下层压。在层压之后，T 2MAX 2将第二介电层的延展性约束为至少D 2。 T 2MAX取决于D 2和在由第二介电层组成的第二电介质材料上。

5. 发明授权

US07329816B2 Electronic package with optimized lamination process 有权
标题翻译：电子封装具有优化的层压工艺
公开(公告)号：US07329816B2
公开(公告)日：2008-02-12
申请号：US11148890
申请日：2005-06-08
申请人： Donald S. Farquhar , James D. Herard , Michael J. Klodowski , David Questad , Der-jin Woan
发明人： Donald S. Farquhar , James D. Herard , Michael J. Klodowski , David Questad , Der-jin Woan
IPC分类号： H05K1/16
CPC分类号： H05K3/4641 , H01L21/4853 , H01L21/4857 , H01L23/3735 , H01L23/49822 , H01L23/49894 , H01L24/16 , H01L2224/13099 , H01L2224/16225 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01068 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/15311 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/351 , H05K1/0271 , H05K1/114 , H05K3/429 , H05K3/4602 , H05K3/4608 , H05K3/4623 , H05K3/4626 , H05K3/4632 , H05K3/4688 , H05K2201/0141 , H05K2201/015 , H05K2201/0191 , H05K2201/0209 , H05K2201/068 , H05K2201/09509 , H05K2201/09536 , H05K2201/09554 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , H05K2203/061 , H05K2203/068 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49163 , Y10T29/49165 , H01L2924/00
摘要： An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T1MIN and a maximum temperature T1MAX. T1MAX constrains the ductility of the first dielectric layer to be at least D1 following the laminating. T1MAX depends on D1 and on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T2MIN and a maximum temperature T2MAX. T2MAX constrains the ductility of the second dielectric layer to be at least D2 following the laminating. T2MAX depends on D2 and on a second dielectric material comprised by the second dielectric layer.
摘要翻译：电子封装和形成方法。提供具有第一和第二相对表面的导热层。第一电介质层在加压下被层压在导热层的第一相对表面上，温度在最低温度T 1 1MIN和最高温度T 1MAX之间。在层压之后，T 1MAX 3将第一介电层的延展性约束至少为D 1。 T 1MAX取决于D 1和在由第一介电层组成的第一电介质材料上。在加压下将第二电介质层在导热层的第二相对表面上，在最低温度T 2 M 2 N 2和最大温度T 2 MAX之间的温度下层压。在层压之后，T 2MAX 2将第二介电层的延展性约束为至少D 2。 T 2MAX取决于D 2和在由第二介电层组成的第二电介质材料上。

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