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1. 发明授权

US5636133A Efficient generation of fill shapes for chips and packages 失效
标题翻译：有效地生成芯片和封装的填充形状
公开(公告)号：US5636133A
公开(公告)日：1997-06-03
申请号：US445447
申请日：1995-05-19
申请人： Donald G. Chesebro , Young O. Kim , Mark A. Lavin , Daniel N. Maynard
发明人： Donald G. Chesebro , Young O. Kim , Mark A. Lavin , Daniel N. Maynard
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An efficient method for modifying a chip or package design allows for the creation of small shapes without excessive expansion of design data. A computer program takes a physical design, represented in a computer data file, and generates a modified version of the design in which fill shapes have been added. Subsequently, when the modified design is processed, the resulting semiconductor chip or package will contain physical images of the added fill shapes, with the effect of making local pattern density more uniform and hence reducing process-induced variations in feature size and shape.
摘要翻译：修改芯片或封装设计的有效方法允许创建小形状而不会过度扩展设计数据。计算机程序采用计算机数据文件中的物理设计，并生成已添加填充形状的设计的修改版本。随后，当改进的设计被处理时，所得到的半导体芯片或封装将包含所添加的填充形状的物理图像，具有使局部图案密度更均匀并因此减少特征尺寸和形状的工艺引起的变化的效果。

2. 发明授权

US4519128A Method of making a trench isolated device 失效
标题翻译：制造沟槽隔离装置的方法
公开(公告)号：US4519128A
公开(公告)日：1985-05-28
申请号：US539193
申请日：1983-10-05
申请人： Donald G. Chesebro , Francis J. Soychak
发明人： Donald G. Chesebro , Francis J. Soychak
IPC分类号： H01L21/76 , H01L21/28 , H01L21/331 , H01L21/74 , H01L21/762 , H01L29/73 , H01L29/732
CPC分类号： H01L21/743 , H01L21/76232 , H01L29/7325
摘要： A method is provided for making a semiconductor device which includes the steps of forming a first insulating layer on the surface of a semiconductor layer having a given conductivity type, forming an opening in the insulating layer and forming a diffusion region of a conductivity type opposite to that of the given conductivity type at the surface of the semiconductor layer to provide a P-N junction below the surface of the semiconductor layer. A trench is then formed along a given axis in the semiconductor layer having a sidewall passing through the opening and through the P-N junction. A second layer of insulation is formed on the sidewall of the trench, on the first insulating layer and through the opening onto the diffusion region. The second layer of insulation is etched in the direction of the given axis until substantially all of the second layer of the insulation is removed from the opening, and an electrical contact is formed on the diffusion region within the opening. In a preferred embodiment of the invention, the second layer is a dual insulating layer which may include a layer of silicon dioxide grown on the semiconductor layer and a layer of silicon nitride deposited on the layer of silicon dioxide.
摘要翻译：提供一种用于制造半导体器件的方法，该半导体器件包括以下步骤：在具有给定导电类型的半导体层的表面上形成第一绝缘层，在绝缘层中形成开口，并形成与在半导体层的表面具有给定的导电类型，以在半导体层的表面下方提供PN结。然后在具有侧壁通过开口并穿过P-N结的半导体层中沿给定的轴形成沟槽。第二绝缘层形成在沟槽的侧壁上，在第一绝缘层上并通过扩散区上的开口。绝缘层的第二层在给定的轴线的方向被蚀刻，直到绝缘体的基本上所有的第二层从开口去除，并且在开口内的扩散区域上形成电接触。在本发明的优选实施例中，第二层是双重绝缘层，其可以包括在半导体层上生长的二氧化硅层和沉积在二氧化硅层上的氮化硅层。

3. 发明授权

US4632724A Visibility enhancement of first order alignment marks 失效
标题翻译：一阶对准标记的可见度增强
公开(公告)号：US4632724A
公开(公告)日：1986-12-30
申请号：US767316
申请日：1985-08-19
申请人： Donald G. Chesebro , Robert W. Sweetser
发明人： Donald G. Chesebro , Robert W. Sweetser
IPC分类号： G03F9/00 , H01L21/027 , H01L21/30 , H01L21/67 , H01L21/68 , H01L23/544 , H01L21/306 , B29C17/08 , B44C1/22 , C03C15/00
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S438/975
摘要： A method of enhancing first order alignment marks formed in the respective layers of a processed semiconductor wafer in which critical masking steps are carried out. After a given mark is formed, it is tested for visual contrast. If the contrast is insufficient to provide adequate alignment, a block mask is formed on the critical mask. The block mask exposes all of the alignment target areas and protects the product regions of the wafer, and the critical mask only exposes the mark to be enhanced. The mark is then etched for a time period which is a function of the measured visual contrast. This method of selectively enhancing selected ones of the first order alignment marks greatly enhances the utility of such marks, increasing the accuracy of critical masking steps.
摘要翻译：一种增强在其中执行关键掩模步骤的处理的半导体晶片的各个层中形成的一阶对准标记的方法。在形成一个给定的标记后，测试其视觉对比度。如果对比度不足以提供足够的对准，则在临界掩模上形成块掩模。块掩模曝光所有对准目标区域并保护晶片的产品区域，并且临界掩模仅暴露要增强的标记。然后刻蚀标记一段时间，这是所测量的视觉对比度的函数。这种选择性地增强一阶对准标记中的选定的方法大大地增强了这种标记的效用，从而提高了临界掩蔽步骤的准确性。

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