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1. 发明申请

US20080311876A1 Signal Receiver for Wideband Wireless Communication 审中-公开
标题翻译：用于宽带无线通信的信号接收机
公开(公告)号：US20080311876A1
公开(公告)日：2008-12-18
申请号：US11910455
申请日：2006-03-16
申请人： Dominicus M.W. Leenaerts , Cornelis H. Van Berkel
发明人： Dominicus M.W. Leenaerts , Cornelis H. Van Berkel
IPC分类号： H04B1/26
CPC分类号： H04B1/0092 , H04B1/28
摘要： A signal receiver for use in a 60 GHz wireless area network, in which the received RF signal band (100) is converted to a plurality of intermediate frequency (IF) sub-bands (104) and then processing (LPF, AGC, ADC) in the analogue domain of the sub-bands (104) is performed in parallel. As a result, the design requirements of the analogue components are significantly relaxed and it is possible to perform gain control in respect of each sub-band (104), which improves the quality of the received signal.
摘要翻译：一种在60GHz无线区域网络中使用的信号接收机，其中接收的RF信号频带（100）被转换成多个中频（IF）子频带（104），然后处理（LPF，AGC，ADC）在子带（104）的模拟域中并行执行。结果，模拟部件的设计要求显着地松弛，并且可以对每个子带（104）执行增益控制，这提高了接收信号的质量。

2. 发明申请

US20100211749A1 METHOD OF STORING DATA, METHOD OF LOADING DATA AND SIGNAL PROCESSOR 有权
标题翻译：存储数据的方法，数据加载方法和信号处理器
公开(公告)号：US20100211749A1
公开(公告)日：2010-08-19
申请号：US12450819
申请日：2008-04-11
申请人： Cornelis H. Van Berkel
发明人： Cornelis H. Van Berkel
IPC分类号： G06F12/00
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3885
摘要： A method for storing a vector of process data elements (D1, . . . , D8) that have a size of n bits from a register file (RF) into a memory (M) is described. The memory is arranged for storage of a vector of storage data elements in locations (M1, . . . , M5) having a size of m bits, wherein m>n. The method comprises the steps of: exchanging bits (S2) between process data elements in the vector stored in mutually subsequent register elements, the exchanging resulting in a vector of modified data elements (DmI, . . . , Dm8), shuffling (S3) groups of k subsequent bits in the resulting vector, —storing (S4) the resulting shuffled vector of modified data elements as a vector of storage data elements in the memory (M).
摘要翻译：描述了一种用于将具有从寄存器文件（RF）到n存储器（M）的n位大小的处理数据元素（D1，...，D8）的向量存储的方法。存储器被布置用于将存储数据元素的矢量存储在具有m位大小的位置（M1，... M5）中，其中m> n。该方法包括以下步骤：在存储在相互后继的寄存器元件中的向量中交换处理数据元素之间的位（S2），产生修改后的数据元素（DmI，...，Dm8），混洗（S3）在所得到的向量中的k个后续比特的组，将修改的数据元素的所得混洗向量（S4）存储（S4）作为存储器（M）中的存储数据元素的向量。

3. 发明授权

US5005136A Silicon-compiler method and arrangement 失效
标题翻译：硅编译方法和布置
公开(公告)号：US5005136A
公开(公告)日：1991-04-02
申请号：US156392
申请日：1988-02-16
申请人： Cornelis H. Van Berkel , Ronald W. J. J. Saeijs , Cornelis Niessen
发明人： Cornelis H. Van Berkel , Ronald W. J. J. Saeijs , Cornelis Niessen
IPC分类号： G06F9/45 , G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A silicon-compilation method, a silicon-compiler arrangement, an abstract-circuit synthesis module usable in such arrangement, a machine-generated abstract circuit produced by such module, an electronic circuit generated by such method and a reset-free circuit produced by such arrangement. There are described a method and arrangement for silicon compilation. First, an algorithmic procedure to be executed by the electronic circuit is expressed in an imperative concurrent language. This, under execution of lexical, syntactic and semantic analysis is converted to a structure tree as an abstract representation of said procedure. This structure tree then is converted into an abstract circuit, wherein each basic component is a program module and each abstract channel corresponds to a program channel. Thereafter, the abstract circuit is converted into a concrete circuit, while obeying timing-organization constraints, circuitry-type constraints and technology constraints. Finally, the concrete circuit is converted into a very large-scale integrated-circuit layout.

4. 发明授权

US5903570A Timing circuit using handshake connections 失效
标题翻译：定时电路使用握手连接
公开(公告)号：US5903570A
公开(公告)日：1999-05-11
申请号：US673783
申请日：1996-06-20
申请人： Cornelis H. Van Berkel
发明人： Cornelis H. Van Berkel
IPC分类号： G06F13/42 , G06F5/06 , H03K5/00 , H04L7/00 , H04J3/06
CPC分类号： G06F5/06
摘要： In an asynchronous circuit (i.e. a circuit without a clock coupled to all parts of the circuit) synchronization is provided by a network of synchronization circuits. Handshake connections exist between pairs of synchronization circuits. These connections comprise a single conductor on which a first synchronization circuit realizes a first potential transition which serves as an attention signal for a second synchronization circuit. The second synchronization circuit applies the attention signal to other synchronization circuits by forming similar attention signals on one or more further conductors. After acknowledgement of said attention signals, the synchronization circuit acknowledges the original attention signal by returning the potential on the conductor to its level prior to the original attention signal.
摘要翻译：在异步电路（即没有与电路的所有部分相连的时钟的电路）中，同步由同步电路网络提供。成对的同步电路之间存在握手连接。这些连接包括单个导体，第一同步电路在其上实现用作第二同步电路的注意信号的第一电位跃迁。第二同步电路通过在一个或多个其它导体上形成类似的注意信号来将注意信号施加到其它同步电路。在确认了所述注意信号之后，同步电路通过将导体上的电位返回其原始注意信号之前的电平来确认原始注意信号。

5. 发明授权

US5590275A Method for testing an integrated circuitry and an integrated circuit having a plurality of functional components and having junction/switch test components in interconnecting channels between functional components 失效
标题翻译：用于测试集成电路的方法和具有多个功能部件并且在功能部件之间的互连通道中具有连接/开关测试部件的集成电路
公开(公告)号：US5590275A
公开(公告)日：1996-12-31
申请号：US389083
申请日：1995-02-14
申请人： Cornelis H. Van Berkel , Maria E. Roncken , Ronald W. J. J. Saeijs
发明人： Cornelis H. Van Berkel , Maria E. Roncken , Ronald W. J. J. Saeijs
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/267 , G06F11/34
CPC分类号： G01R31/318558 , G06F11/267 , G06F11/221 , G06F11/2221
摘要： The invention proposes a testing method and associated arrangement for electronic circuitry that combines functional components that are interconnected by handshake channels. Various of such channels are now provided with an inbreaking junction and an outbreaking switch as a test component pair. The junction has two passive ports and one active port. The switch has one passive port and two active ports that are selected through a passive control port. In this way inbreaking into and outbreaking from the channel is rendered feasible. Now inbreaking is done on a first channel, and outbreaking on a second channel, so that thereby all components are tested that lie between the first channel's junction and the second channel's switch.
摘要翻译：本发明提出了一种电子电路的测试方法和相关布置，其组合由握手通道互连的功能部件。各种这样的通道现在设置有断开连接点和作为测试部件对的断开开关。连接点有两个被动端口和一个活动端口。交换机有一个被动端口和两个通过被动控制端口选择的活动端口。以这种方式，从渠道突破和突破是可行的。现在在第一通道上进行断开，并且在第二通道上进行断开，从而测试位于第一通道的结和第二通道的开关之间的所有部件。

6. 发明授权

US08605719B2 Circuit with network of message distributor circuits 有权
标题翻译：电路与消息分配器电路网络
公开(公告)号：US08605719B2
公开(公告)日：2013-12-10
申请号：US12452643
申请日：2008-07-07
申请人： Cornelis H. Van Berkel
发明人： Cornelis H. Van Berkel
IPC分类号： H04L12/50 , H04Q11/00 , G06F3/00 , G06F5/00 , G06F13/00 , H04L12/56 , G06F15/17 , G06F15/173 , G06F15/163
CPC分类号： H04L49/15 , G06F9/5027 , G06F15/16 , G06F15/163 , G06F15/17 , G06F15/173 , G06F15/17356 , G06F15/17393 , H04L47/10 , H04L47/266 , H04L47/30 , H04L49/10 , H04L49/101 , H04L49/1507 , H04L49/25 , H04L49/506
摘要： Source circuits (10) produce messages that may each be processed by any one of a plurality of processing circuits (14). A network of distributor circuits is provided between the source circuits and the processing circuits (14). Local decisions by the distributor circuits in the network decide for each message to which one of the processing circuits the message will be routed. Messages are supplied to at least two parallel distributor circuits. These distributor circuits (12a) select from further distributor circuits (12b) in the network on the basis of current availability of individual ones of the further distributor circuits (12b). The respective messages are in turn forwarded from the selected further distributor circuits (12b) to data processing circuits (14) along routes selected by the selected further distributor circuits (12b) on the basis of current availability of the data processing circuits (14) and/or subsequent distributor circuits (12c) in the network.
摘要翻译：源电路（10）产生可以由多个处理电路（14）中的任何一个处理的消息。在源电路和处理电路（14）之间提供分配器电路网络。网络中的分配器电路的本地决定决定了消息将被路由到哪个处理电路的每个消息。消息提供给至少两个并行分配器电路。这些分配器电路（12a）基于其他分配器电路（12b）中的各个的当前可用性从网络中的其它分配器电路（12b）中进行选择。根据数据处理电路（14）的当前可用性，各个消息依次由所选择的另外的分配器电路（12b）选择的路径从所选择的另外的分配器电路（12b）转发到数据处理电路（14），以及 /或后续的分配器电路（12c）。

7. 发明授权

US08489825B2 Method of storing data, method of loading data and signal processor 有权
标题翻译：存储数据的方法，数据加载方法和信号处理器
公开(公告)号：US08489825B2
公开(公告)日：2013-07-16
申请号：US12450819
申请日：2008-04-11
申请人： Cornelis H. Van Berkel
发明人： Cornelis H. Van Berkel
IPC分类号： G06F12/00
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3885
摘要： A method for storing a vector of process data elements (D1, . . . , D8) that have a size of n bits from a register file (RF) into a memory (M) is described. The memory is arranged for storage of a vector of storage data elements in locations (M1, . . . , M5) having a size of m bits, wherein m>n. The method comprises the steps of: exchanging bits (S2) between process data elements in the vector stored in mutually subsequent register elements, the exchanging resulting in a vector of modified data elements (DmI, . . . , Dm8), shuffling (S3) groups of k subsequent bits in the resulting vector, —storing (S4) the resulting shuffled vector of modified data elements as a vector of storage data elements in the memory (M).
摘要翻译：描述了一种用于将具有从寄存器文件（RF）到n存储器（M）的n位大小的处理数据元素（D1，...，D8）的向量存储的方法。存储器被布置用于将存储数据元素的矢量存储在具有m位大小的位置（M1，... M5）中，其中m> n。该方法包括以下步骤：在存储在相互后继的寄存器元件中的向量中交换处理数据元素之间的位（S2），产生修改后的数据元素（DmI，...，Dm8），混洗（S3）在所得到的向量中的k个后续比特的组，将修改的数据元素的所得混洗向量（S4）存储（S4）作为存储器（M）中的存储数据元素的向量。

8. 发明申请

US20110044328A1 CIRCUIT WITH NETWORK OF MESSAGE DISTRIBUTOR CIRCUITS 有权
标题翻译：具有消息分发电路网络的电路
公开(公告)号：US20110044328A1
公开(公告)日：2011-02-24
申请号：US12452643
申请日：2008-07-07
申请人： Cornelis H. Van Berkel
发明人： Cornelis H. Van Berkel
IPC分类号： H04L12/50
CPC分类号： H04L49/15 , G06F9/5027 , G06F15/16 , G06F15/163 , G06F15/17 , G06F15/173 , G06F15/17356 , G06F15/17393 , H04L47/10 , H04L47/266 , H04L47/30 , H04L49/10 , H04L49/101 , H04L49/1507 , H04L49/25 , H04L49/506
摘要： Source circuits (10) produce messages that may each be processed by any one of a plurality of processing circuits (14). A network of distributor circuits is provided between the source circuits and the processing circuits (14). Local decisions by the distributor circuits in the network decide for each message to which one of the processing circuits the message will be routed. Messages are supplied to at least two parallel distributor circuits. These distributor circuits (12a) select from further distributor circuits (12b) in the network on the basis of current availability of individual ones of the further distributor circuits (12b). The respective messages are in turn forwarded from the selected further distributor circuits (12b) to data processing circuits (14) along routes selected by the selected further distributor circuits (12b) on the basis of current availability of the data processing circuits (14) and/or subsequent distributor circuits (12c) in the network.
摘要翻译：源电路（10）产生可以由多个处理电路（14）中的任何一个处理的消息。在源电路和处理电路（14）之间提供分配器电路网络。网络中的分配器电路的本地决定决定了消息将被路由到哪个处理电路的每个消息。消息提供给至少两个并行分配器电路。这些分配器电路（12a）基于其他分配器电路（12b）中的各个的当前可用性从网络中的其它分配器电路（12b）中进行选择。根据数据处理电路（14）的当前可用性，各个消息依次由所选择的另外的分配器电路（12b）选择的路径从所选择的另外的分配器电路（12b）转发到数据处理电路（14），以及 /或后续的分配器电路（12c）。

9. 发明授权

US08135897B2 Memory architecture 有权
标题翻译：内存架构
公开(公告)号：US08135897B2
公开(公告)日：2012-03-13
申请号：US12227344
申请日：2007-05-14
申请人： Cornelis H. Van Berkel
发明人： Cornelis H. Van Berkel
IPC分类号： G06F12/06
CPC分类号： G06F13/1694 , Y02D10/14
摘要： A memory architecture is presented. The memory architecture comprises a first memory and a second memory. The first memory has at least a bank with a first width addressable by a single address. The second memory has a plurality of banks of a second width, said banks being addressable by components of an address vector. The second width is at most half of the first width. The first memory and the second memory are coupled selectively and said first memory and second memory are addressable by an address space. The invention further provides a method for transposing a matrix using the memory architecture comprising following steps. In the first step the matrix elements are moved from the first memory to the second memory. In the second step a set of elements arranged along a warped diagonal of the matrix is loaded into a register. In the fourth step the set of elements stored in the register are rotated until the element originating from the first row of the matrix is in a first location of the register. In the fifth step the rotated set of elements are stored in the second memory to obtain a transposed warped diagonal. The second to fifth steps are repeated with the subsequent warp diagonals until matrix transposition is complete.
摘要翻译：介绍了一种内存架构。存储器架构包括第一存储器和第二存储器。第一个存储器至少具有可由单个地址寻址的第一宽度的存储区。第二存储器具有多个第二宽度的组，所述组可由地址向量的组件寻址。第二宽度是第一宽度的至多一半。第一存储器和第二存储器被选择性地耦合，并且所述第一存储器和第二存储器可由地址空间寻址。本发明还提供一种使用存储器架构来转置矩阵的方法，包括以下步骤。在第一步中，矩阵元素从第一存储器移动到第二存储器。在第二步中，沿着矩阵的翘曲对角线布置的一组元件被加载到寄存器中。在第四步骤中，存储在寄存器中的元素集合被旋转，直到来自矩阵的第一行的元素处于寄存器的第一位置。在第五步骤中，将旋转的元件组存储在第二存储器中以获得转置的翘曲对角线。第二至第五步骤随后续的经向对角线重复，直到矩阵转置完成。

10. 发明申请

US20090300310A1 Memory Architecture 有权
标题翻译：内存架构
公开(公告)号：US20090300310A1
公开(公告)日：2009-12-03
申请号：US12227344
申请日：2007-05-14
申请人： Cornelis H. Van Berkel
发明人： Cornelis H. Van Berkel
IPC分类号： G06F12/02
CPC分类号： G06F13/1694 , Y02D10/14
摘要： A memory architecture is presented. The memory architecture comprises a first memory and a second memory. The first memory has at least a bank with a first width addressable by a single address. The second memory has a plurality of banks of a second width, said banks being addressable by components of an address vector. The second width is at most half of the first width. The first memory and the second memory are coupled selectively and said first memory and second memory are addressable by an address space. The invention further provides a method for transposing a matrix using the memory architecture comprising following steps. In the first step the matrix elements are moved from the first memory to the second memory. In the second step a set of elements arranged along a warped diagonal of the matrix is loaded into a register. In the fourth step the set of elements stored in the register are rotated until the element originating from the first row of the matrix is in a first location of the register. In the fifth step the rotated set of elements are stored in the second memory to obtain a transposed warped diagonal. The second to fifth steps are repeated with the subsequent warp diagonals until matrix transposition is complete.
摘要翻译：介绍了一种内存架构。存储器架构包括第一存储器和第二存储器。第一个存储器至少具有可以由单个地址寻址的第一宽度的存储体。第二存储器具有多个第二宽度的组，所述组可由地址向量的组件寻址。第二宽度是第一宽度的至多一半。第一存储器和第二存储器被选择性地耦合，并且所述第一存储器和第二存储器可由地址空间寻址。本发明还提供一种使用存储器架构来转置矩阵的方法，包括以下步骤。在第一步中，矩阵元素从第一存储器移动到第二存储器。在第二步中，沿着矩阵的翘曲对角线布置的一组元件被加载到寄存器中。在第四步骤中，存储在寄存器中的元素集合被旋转，直到来自矩阵的第一行的元素处于寄存器的第一位置。在第五步骤中，将旋转的元件组存储在第二存储器中以获得转置的翘曲对角线。第二至第五步骤随后续的经向对角线重复，直到矩阵转置完成。

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