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1. 发明授权

US09419108B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09419108B2
公开(公告)日：2016-08-16
申请号：US14406904
申请日：2012-08-17
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Chao Zhao , Tianchun Ye
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Chao Zhao , Tianchun Ye
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/785 , H01L29/7855
摘要： One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.
摘要翻译：本发明的一个实施例提供了一种用于制造半导体结构的方法，其包括：在半导体衬底上形成栅极叠层并去除位于栅极叠层两侧的衬底的部分; 在所述栅极堆叠的侧壁上以及在所述栅极堆叠下的所述衬底的所述部分的侧壁上形成侧壁间隔物; 在所述栅极堆叠的两侧上在所述衬底的部分中形成掺杂区域，以及形成覆盖整个半导体结构的第一介电层; 选择性地去除所述栅极堆叠的部分和所述第一介电层的部分以形成沟道区域开口和源极/漏极区域开口; 在沟道区域开口的侧壁上形成高K电介质层; 并且实现外延工艺以形成跨越沟道区域开口和源极/漏极区域开口的连续翅片结构。

2. 发明申请

US20150311319A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150311319A1
公开(公告)日：2015-10-29
申请号：US14406904
申请日：2012-08-17
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Chao Zhao , Tianchun Ye
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Chao Zhao , Tianchun Ye
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/785 , H01L29/7855
摘要： One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.
摘要翻译：本发明的一个实施例提供了一种用于制造半导体结构的方法，其包括：在半导体衬底上形成栅极叠层并去除位于栅极叠层两侧的衬底的部分; 在所述栅极堆叠的侧壁上以及在所述栅极堆叠下的所述衬底的所述部分的侧壁上形成侧壁间隔物; 在所述栅极堆叠的两侧上在所述衬底的部分中形成掺杂区域，以及形成覆盖整个半导体结构的第一介电层; 选择性地去除所述栅极堆叠的部分和所述第一介电层的部分以形成沟道区域开口和源极/漏极区域开口; 在沟道区域开口的侧壁上形成高K电介质层; 并且实现外延工艺以形成跨越沟道区域开口和源极/漏极区域开口的连续翅片结构。

3. 发明申请

US20130037859A1 SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其编程方法
公开(公告)号：US20130037859A1
公开(公告)日：2013-02-14
申请号：US13321852
申请日：2011-08-12
申请人： Huicai Zhong , Qingqing Liang , Chao Zhao , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Chao Zhao , Huilong Zhu
IPC分类号： H01L27/10 , H01L21/326 , H01L23/522 , H01L29/788 , H01L29/92 , H01L23/525
CPC分类号： H01L23/481 , H01L23/525 , H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method for programming the same are provided. The semiconductor device comprises: a semiconductor substrate with an interconnect formed therein; a Through-Silicon Via (TSV) penetrating through the semiconductor substrate; and a programmable device which can be switched between on and off states, the TSV being connected to the interconnect by the programmable device. The present invention is beneficial in improving flexibility of TSV application.
摘要翻译：提供了半导体器件及其编程方法。半导体器件包括：其中形成有互连的半导体衬底; 穿透半导体衬底的透硅通孔（TSV）; 以及可以在导通和关断状态之间切换的可编程器件，TSV通过可编程器件连接到互连。本发明有利于提高TSV应用的灵活性。

4. 发明授权

US08557677B2 Stack-type semiconductor device and method for manufacturing the same 有权
标题翻译：叠层型半导体器件及其制造方法
公开(公告)号：US08557677B2
公开(公告)日：2013-10-15
申请号：US13120792
申请日：2011-02-17
申请人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
IPC分类号： H01L21/30
CPC分类号： H01L25/50 , H01L21/6835 , H01L23/481 , H01L25/0657 , H01L2221/68327 , H01L2221/68359 , H01L2221/68363 , H01L2221/68368 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stack-type semiconductor device includes a semiconductor substrate; and a plurality of wafer assemblies arranged in various levels on the semiconductor substrate, in which the wafer assembly in each level includes an active part and an interconnect part, and the active part and the interconnect part each have conductive through vias, wherein the conductive through vias in the active part are aligned with the conductive through vias in the interconnect part in a vertical direction, so that the active part in each level is electrically coupled with the active part in the previous level and/or the active part in the next level by the conductive through vias. Such a stack-type semiconductor device and the related methods can be applied in a process after the FEOL or in a semiconductor chip packaging process and provide a 3-dimensional semiconductor device of high integration and high reliability.
摘要翻译：堆叠型半导体器件包括半导体衬底; 以及在所述半导体衬底上以各种级别布置的多个晶片组件，其中每个级中的所述晶片组件包括有源部分和互连部分，并且所述有源部分和所述互连部件各自具有导电通孔，其中所述导电通孔有源部分中的通孔在垂直方向上与互连部分中的导电通孔对准，使得每个电平中的有源部分与先前电平中的有源部分和/或下一级的有源部分电耦合通过导电通孔。这种叠层型半导体器件及相关方法可以在FEOL之后的工艺中或半导体芯片封装工艺中应用，并提供高集成度和高可靠性的三维半导体器件。

5. 发明申请

US20120112358A1 STACK-TYPE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：堆叠型半导体器件及其制造方法
公开(公告)号：US20120112358A1
公开(公告)日：2012-05-10
申请号：US13120792
申请日：2011-02-17
申请人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L25/50 , H01L21/6835 , H01L23/481 , H01L25/0657 , H01L2221/68327 , H01L2221/68359 , H01L2221/68363 , H01L2221/68368 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stack-type semiconductor device includes a semiconductor substrate; and a plurality of wafer assemblies arranged in various levels on the semiconductor substrate, in which the wafer assembly in each level includes an active part and an interconnect part, and the active part and the interconnect part each have conductive through vias, wherein the conductive through vias in the active part are aligned with the conductive through vias in the interconnect part in a vertical direction, so that the active part in each level is electrically coupled with the active part in the previous level and/or the active part in the next level by the conductive through vias. Such a stack-type semiconductor device and the related methods can be applied in a process after the FEOL or in a semiconductor chip packaging process and provide a 3-dimensional semiconductor device of high integration and high reliability.
摘要翻译：堆叠型半导体器件包括半导体衬底; 以及在所述半导体衬底上以各种级别布置的多个晶片组件，其中每个级中的所述晶片组件包括有源部分和互连部分，并且所述有源部分和所述互连部件各自具有导电通孔，其中所述导电通孔有源部分中的通孔在垂直方向上与互连部分中的导电通孔对准，使得每个电平中的有源部分与先前电平中的有源部分和/或下一级的有源部分电耦合通过导电通孔。这种叠层型半导体器件及相关方法可以在FEOL之后的工艺中或半导体芯片封装工艺中应用，并提供高集成度和高可靠性的三维半导体器件。

6. 发明申请

US20150236134A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20150236134A1
公开(公告)日：2015-08-20
申请号：US14412237
申请日：2012-07-18
申请人： Huicai Zhong , Qingqing Liang , Chao Zhao
发明人： Huicai Zhong , Qingqing Liang , Chao Zhao
IPC分类号： H01L29/66
CPC分类号： H01L29/66795 , H01L21/268 , H01L21/76283 , H01L29/665 , H01L29/785
摘要： A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.
摘要翻译：提供一种制造FinFET半导体器件的方法，其中半导体鳍片形成为与并行布置的栅极相交的平行布置。沉积多晶硅层，然后转换为单晶硅层，使得单晶硅层和半导体鳍片本质上是集成的，即半导体鳍片中的源极/漏极区域被升高，并且顶部区域半导体鳍片延伸。随后，将半导体鳍片顶部上方的单晶硅层转换为金属硅化物，以形成源极/漏极区域接触。本发明中的源极/漏极区域的接触面积大于传统的FinFET的面积，这在以后的过程中降低了接触电阻并且有利于形成自对准的金属插塞。

7. 发明授权

US08748983B2 Embedded source/drain MOS transistor 有权
标题翻译：嵌入式源极/漏极MOS晶体管
公开(公告)号：US08748983B2
公开(公告)日：2014-06-10
申请号：US13380828
申请日：2011-08-12
申请人： Huicai Zhong , Chao Zhao , Qingqing Liang
发明人： Huicai Zhong , Chao Zhao , Qingqing Liang
IPC分类号： H01L27/12 , H01L21/70
CPC分类号： H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate.
摘要翻译：提供一种嵌入式源极/漏极MOS晶体管及其形成方法。嵌入式源极/漏极MOS晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及在源极/漏极叠层的上表面被暴露的栅极结构的两侧嵌入在半导体衬底中的源极/漏极堆叠，其中源极/漏极叠层包括电介质层和介电层上方的半导体层。本发明可以切断从源极区域和漏极区域到半导体衬底的漏电流的路径，从而减少从源极区域和漏极区域到半导体衬底的漏电流。

8. 发明申请

US20130228893A1 TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译： TRENCH隔离结构及其形成方法
公开(公告)号：US20130228893A1
公开(公告)日：2013-09-05
申请号：US13145301
申请日：2011-04-22
申请人： Huicai Zhong , Chao Zhao , Qingqing Liang
发明人： Huicai Zhong , Chao Zhao , Qingqing Liang
IPC分类号： H01L21/762 , H01L29/02
CPC分类号： H01L21/76224 , H01L21/76232 , H01L29/02
摘要： A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed on the surface of the semiconductor substrate and filled with a dielectric layer, wherein the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved.
摘要翻译：提供了沟槽隔离结构及其形成方法。沟槽隔离结构包括：半导体衬底和形成在半导体衬底的表面上并填充有电介质层的沟槽，其中电介质层的材料是结晶材料。通过使用本发明，可以减小纹路的尺寸，并且可以提高器件性能。

9. 发明申请

US20120273886A1 EMBEDDED SOURCE/DRAIN MOS TRANSISTOR AND METHOD FOR FORMING THE SAME 有权
标题翻译：嵌入式源/漏极MOS晶体管及其形成方法
公开(公告)号：US20120273886A1
公开(公告)日：2012-11-01
申请号：US13380828
申请日：2011-08-12
申请人： Huicai Zhong , Chao Zhao , Qingqing Liang
发明人： Huicai Zhong , Chao Zhao , Qingqing Liang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate.
摘要翻译：提供一种嵌入式源极/漏极MOS晶体管及其形成方法。嵌入式源极/漏极MOS晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及在源极/漏极叠层的上表面被暴露的栅极结构的两侧嵌入在半导体衬底中的源极/漏极堆叠，其中源极/漏极叠层包括电介质层和介电层上方的半导体层。本发明可以切断从源极区域和漏极区域到半导体衬底的漏电流的路径，从而减少从源极区域和漏极区域到半导体衬底的漏电流。

10. 发明申请

US20120149181A1 METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER 有权
标题翻译：制造半导体波形的方法
公开(公告)号：US20120149181A1
公开(公告)日：2012-06-14
申请号：US13201125
申请日：2011-02-25
申请人： Huicai Zhong , Qingqing Liang , Chao Zhao
发明人： Huicai Zhong , Qingqing Liang , Chao Zhao
IPC分类号： H01L21/24
CPC分类号： H01L21/3221
摘要： There is provided a method for manufacturing a semiconductor wafer, comprising: performing heating so that metals dissolve into semiconductors of the wafer to form a semiconductor-metal compound; and performing cooling so that the formed semiconductor-metal compound retrogradely melt to form a mixture of the metals and the semiconductors. According to embodiments of the present invention, it is possible to achieve wafers of a high purity applicable to the semiconductor manufacture.
摘要翻译：提供了一种制造半导体晶片的方法，包括：进行加热，使得金属溶解到晶片的半导体中以形成半导体 - 金属化合物; 并进行冷却，使得所形成的半导体 - 金属化合物逆向熔融以形成金属和半导体的混合物。根据本发明的实施例，可以实现适用于半导体制造的高纯度晶片。

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