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    • 3. 发明授权
    • Voltage based data driving circuits and organic light emitting displays using the same
    • 基于电压的数据驱动电路和使用其的有机发光显示器
    • US07893898B2
    • 2011-02-22
    • US11491910
    • 2006-07-25
    • Bo Yong ChungDo Hyung RyuOh Kyong Kwon
    • Bo Yong ChungDo Hyung RyuOh Kyong Kwon
    • G09G3/32
    • G09G3/3233G09G3/3291G09G2300/0819G09G2300/0852G09G2300/0861G09G2310/0251G09G2310/0262G09G2310/027G09G2320/043
    • A data driving circuit for driving pixels of a display to display images with uniform brightness may include a gamma voltage unit that generates gray scale voltages, a digital-analog converter that selects, as a data signal, one of the gray scale voltages using first data, a decoder that generates second data using the first data, a latch for storing the first data and the second data, a current sink that receives a predetermined current from the pixel during a first partial period of a complete period for driving the pixel based on the selected gray scale voltage, a voltage controller that controls a voltage value of the data signal using the second data and a compensation voltage generated based on the predetermined current, and a switching unit that supplies the data signal to the pixel during any partial period of the complete period elapsing after the first partial period.
    • 用于驱动显示器的像素以显示具有均匀亮度的图像的数据驱动电路可以包括产生灰度级电压的伽马电压单元,数模转换器,其使用第一数据选择灰度级电压之一作为数据信号 ,使用第一数据产生第二数据的解码器,用于存储第一数据和第二数据的锁存器,在基于驱动像素的完整周期的第一部分周期期间从像素接收预定电流的电流宿,基于 所选择的灰度级电压,使用第二数据控制数据信号的电压值的电压控制器和基于预定电流产生的补偿电压;以及切换单元,其在任何部分期间内将数据信号提供给像素 第一个部分时期之后的整个时期过去了。
    • 8. 发明授权
    • Demultiplexing circuit, light emitting display using the same, and driving method thereof
    • 解复用电路,使用其的发光显示器及其驱动方法
    • US08199079B2
    • 2012-06-12
    • US11197752
    • 2005-08-03
    • Yang Wan KimYong Sung ParkBo Yong Chung
    • Yang Wan KimYong Sung ParkBo Yong Chung
    • G09G3/30
    • G09G3/3233G09G2300/0819G09G2300/0842G09G2300/0861G09G2310/0248G09G2310/0262G09G2310/0297G09G2320/043
    • A demultiplexing circuit, a light emitting display using the same, and a driving method thereof, in which the number of output lines provided in a data driver is reduced. The light emitting display includes: a scan driver for supplying scan signals to scan lines in sequence; a data driver provided with a plurality of output lines and for supplying a plurality of data signals to the respective output lines while the scan signals are supplied; an image displaying part comprising a plurality of pixels placed in regions sectioned by the scan lines and a plurality of data lines; a plurality of demultiplexers, each of the demultiplexers coupling a respective one the output lines and having a plurality of data transistors adapted to supply a respective one of the data signals from the respective one of the output lines to more than one of the plurality of data lines; and a plurality of initializers having a plurality of initialization transistors adapted to apply a predetermined voltage to each of the plurality of data lines. In one embodiment, at least one of the initialization transistors is kept turned on until a respective one of the data transistors connected to the same data line connected to the at least one of initialization transistors is turned on, thereby supplying a desired data signal to a respective one of the pixels.
    • 解复用电路,使用该解复用电路的发光显示器及其驱动方法,其中提供在数据驱动器中的输出线的数量减少。 发光显示器包括:扫描驱动器,用于依次向扫描线提供扫描信号; 提供有多条输出线的数据驱动器,并且在提供扫描信号的同时将多条数据信号提供给各个输出线; 图像显示部分,包括放置在由扫描线分割的区域中的多个像素和多个数据线; 多个解复用器,每个解复用器将相应的一个输出线耦合并且具有多个数据晶体管,其适于将数据信号中的相应一个从相应的输出线提供给多个数据中的多于一个的数据 线条 以及具有多个初始化晶体管的多个初始化器,其适于对所述多条数据线中的每一条线施加预定电压。 在一个实施例中,至少一个初始化晶体管保持导通,直到连接到连接到初始化晶体管中的至少一个的相同数据线的数据晶体管的相应一个导通,从而将所需的数据信号提供给 相应的一个像素。
    • 9. 发明授权
    • Emission driver and electroluminescent display including such an emission driver
    • 发射驱动器和电致发光显示器,包括这种发射驱动器
    • US07982699B2
    • 2011-07-19
    • US11896023
    • 2007-08-29
    • Bo Yong Chung
    • Bo Yong Chung
    • G09G3/30G09G3/32
    • G09G3/2014G09G3/3258G09G3/3266G09G2300/0866G09G2310/0286
    • An emission driver may include a first signal processor adapted to receive a clock signal, an input signal and an inverse input signal, and to generate a first output signal, a second signal processor adapted to receive the first output signal, an inverse clock signal and negative feedback signals, and to generate a second output signal, a third signal processor adapted to receive the second output signal and the input signal, and to generate a third output signal that is an inverse of the second output signal, a fourth signal processor adapted to receive the third output signal, and to generate a fourth output signal that is an inverse of the third output signal, and a fifth signal processor adapted to receive the fourth output signal, and to output a fifth output signal that is an inverse of the fourth output signal, wherein the negative feedback signals include the fourth and fifth output signals.
    • 发射驱动器可以包括适于接收时钟信号,输入信号和反相输入信号的第一信号处理器,并且产生第一输出信号,适于接收第一输出信号的第二信号处理器,反时钟信号和 负反馈信号,并产生第二输出信号,第三信号处理器,适于接收第二输出信号和输入信号,并产生第二输出信号的第三输出信号,第四信号处理器适配 接收第三输出信号,并产生与第三输出信号相反的第四输出信号;以及第五信号处理器,适于接收第四输出信号,并输出第五输出信号 第四输出信号,其中负反馈信号包括第四和第五输出信号。
    • 10. 发明授权
    • Logic gates, scan drivers and organic light emitting displays using the same
    • 逻辑门,扫描驱动器和使用其的有机发光显示器
    • US07535260B2
    • 2009-05-19
    • US11783014
    • 2007-04-05
    • Bo Yong Chung
    • Bo Yong Chung
    • G11C8/00H03K19/082H03K19/094
    • G09G3/3266H03K19/0013H03K19/09441
    • A logic gate includes a first driver connected to a first power source, a first control transistor connected between a first node and a second power source to control a voltage of the first node, a second driver connected between a gate electrode of the first control transistor and the second power source, a third driver connected between the first power source and the second power source, a second control transistor connected between the third driver and the second power source, and having a first electrode connected to an output terminal, and a fourth driver arranged between a gate electrode of the second control transistor and the second power source, wherein the first control transistor, the second control transistor and each transistor of the first driver, the second driver, the third driver and the fourth driver are PMOS transistors.
    • 逻辑门包括连接到第一电源的第一驱动器,连接在第一节点和第二电源之间的第一控制晶体管,以控制第一节点的电压;连接在第一控制晶体管的栅电极之间的第二驱动器 和第二电源,连接在第一电源和第二电源之间的第三驱动器,连接在第三驱动器和第二电源之间的第二控制晶体管,并且具有连接到输出端子的第一电极,以及第四驱动器 布置在第二控制晶体管的栅电极和第二电源之间的驱动器,其中第一驱动器,第二驱动器,第三驱动器和第四驱动器的第一控制晶体管,第二控制晶体管和每个晶体管是PMOS晶体管。