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1. 发明公开

US20230352584A1 TECHNOLOGIES FOR TRANSISTORS WITH A FERROELECTRIC GATE DIELECTRIC 审中-公开
公开(公告)号：US20230352584A1
公开(公告)日：2023-11-02
申请号：US17734372
申请日：2022-05-02
申请人： Dmitri Evgenievich Nikonov , Chia-Ching Lin , Uygar E. Avci , Tanay A. Gosavi , Raseong Kim , Ian Alexander Young , Hai Li , Ashish Verma Penumatcha , Ramamoorthy Ramesh , Darrell G. Schlom
发明人： Dmitri Evgenievich Nikonov , Chia-Ching Lin , Uygar E. Avci , Tanay A. Gosavi , Raseong Kim , Ian Alexander Young , Hai Li , Ashish Verma Penumatcha , Ramamoorthy Ramesh , Darrell G. Schlom
IPC分类号： H01L29/78 , H01L29/51 , H01L29/66 , H10B51/30
CPC分类号： H01L29/78391 , H01L29/516 , H01L29/6684 , H10B51/30
摘要： Technologies for a transistor with a ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a ferroelectric gate dielectric that is lattice matched to the channel of the transistor. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one transistor memory cell.

2. 发明公开

US20230353157A1 PEROVSKITE-BASED MAGNETOELECTRIC SPIN-ORBIT LOGIC DEVICES 审中-公开
公开(公告)号：US20230353157A1
公开(公告)日：2023-11-02
申请号：US17733166
申请日：2022-04-29
申请人： Tanay A. Gosavi , Chia-Ching Lin , Sasikanth Manipatruni , Dmitri Evgenievich Nikonov , Ian Alexander Young , Ramamoorthy Ramesh , Darrell G. Schlom , Megan E. Holtz , Rachel A. Steinhardt
发明人： Tanay A. Gosavi , Chia-Ching Lin , Sasikanth Manipatruni , Dmitri Evgenievich Nikonov , Ian Alexander Young , Ramamoorthy Ramesh , Darrell G. Schlom , Megan E. Holtz , Rachel A. Steinhardt
IPC分类号： H03K19/18 , H01L43/10 , H01L43/02 , H01L27/22
CPC分类号： H03K19/18 , H01L43/10 , H01L43/02 , H01L27/22
摘要： Magnetoelectric spin-orbit logic (MESO) devices comprise a magnetoelectric switch capacitor coupled to a spin-orbit coupling structure. The logic state of the MESO device is represented by the magnetization orientation of the ferromagnet of the magnetoelectric switch capacitor and the spin-orbit coupling structure converts the magnetization orientation of the ferromagnet to an output current. MESO devices in which all or at least some of the constituent layers of the device are perovskite materials can provide advantages such as improved control over the manufacturing of MESO devices and high quality interfaces between MESO layers due to the lattice matching of perovskite materials.

3. 发明授权

US06642539B2 Epitaxial template and barrier for the integration of functional thin film metal oxide heterostructures on silicon 失效
标题翻译：外延模板和屏障，用于在硅上整合功能性薄膜金属氧化物异质结构
公开(公告)号：US06642539B2
公开(公告)日：2003-11-04
申请号：US10231401
申请日：2002-08-29
申请人： Ramamoorthy Ramesh , Darrell G. Schlom
发明人： Ramamoorthy Ramesh , Darrell G. Schlom
IPC分类号： H01L2912
CPC分类号： H01L27/11502 , G11C11/22 , H01L21/28568 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： A ferroelectric memory cell formed on a monocrystalline silicon underlayer, either an epitaxial silicon contact plug to a transistor source or drain or silicon gate region for which the memory cell forms a non-volatile gate. A conductive barrier layer of doped strontium titanate, whether cationically substituted, such by lanthanum or niobium for strontium and titanium respectively, or anionically deficient, is epitaxially grown over the silicon, and a lower metal oxide electrode layer, a ferroelectric layer and an upper metal oxide electrode layer are epitaxially grown on the barrier layer. No platinum barrier is needed beneath the ferroelectric stack. The invention can be applied to many other functional oxide materials of the Ruddlesden-Popper and devices including micromachined electromechanical (MEM) devices and ferromagnetic tri-layer devices.
摘要翻译：在单晶硅衬底上形成的铁电存储单元，即存储单元形成非易失性栅极的硅晶体管源极或漏极或硅栅极区域的外延硅接触插塞。掺杂的钛酸锶的导电阻挡层，无论是阳离子取代的，如分别用于锶和钛的镧或铌或阴离子缺陷的导电阻挡层在硅上外延生长，并且下部金属氧化物电极层，铁电层和上部金属氧化物电极层在阻挡层上外延生长。铁电堆下方不需要铂金屏障。本发明可以应用于Ruddlesden-Popper的许多其它功能氧化物材料和包括微加工机电（MEM）器件和铁磁性三层器件的器件。

4. 发明申请

US20100002563A1 MEDIA WITH TETRAGONALLY-STRAINED RECORDING LAYER HAVING IMPROVED SURFACE ROUGHNESS 审中-公开
标题翻译：具有改进的表面粗糙度的具有四面体应变记录层的介质
公开(公告)号：US20100002563A1
公开(公告)日：2010-01-07
申请号：US12165851
申请日：2008-07-01
申请人： Byong M. Kim , Jingwei Li , Pu Yu , Donald E. Adams , Ying-Hao Chu , Yevgeny V. Anoikin , Ramamoorthy Ramesh , Li-Peng Wang
发明人： Byong M. Kim , Jingwei Li , Pu Yu , Donald E. Adams , Ying-Hao Chu , Yevgeny V. Anoikin , Ramamoorthy Ramesh , Li-Peng Wang
IPC分类号： G11B9/00 , B32B15/04 , H01L21/00
CPC分类号： G11B9/02 , Y10T428/12535 , Y10T428/12701 , Y10T428/24942
摘要： A media for storing information comprises a substrate, a conductive layer formed over the substrate, and a ferroelectric layer epitaxially formed on the conductive layer. The ferroelectric layer includes an a-lattice constant that is substantially matched to an a-lattice constant of the conductive layer and an average c-lattice constant that is longer than an average c-lattice constant of a bulk-grown ferroelectric layer.
摘要翻译：用于存储信息的介质包括衬底，形成在衬底上的导电层和外延形成在导电层上的铁电层。铁电层包括基本上与导电层的a晶格常数匹配的a晶格常数和长于体积生长的铁电层的平均c-晶格常数的平均c-晶格常数。

5. 发明授权

US06908802B2 Ferroelectric circuit element that can be fabricated at low temperatures and method for making the same 有权
标题翻译：可在低温下制造的铁电电路元件及其制造方法
公开(公告)号：US06908802B2
公开(公告)日：2005-06-21
申请号：US10377971
申请日：2003-02-27
申请人： Ramamoorthy Ramesh
发明人： Ramamoorthy Ramesh
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L27/115 , H01L21/8238
CPC分类号： H01L27/11502 , H01L21/76877 , H01L27/10852 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： A circuit element that includes a ferroelectric device connected to a substrate device. The circuit element is constructed by fabricating the substrate device in a semiconductor substrate and depositing a dielectric layer over the semiconductor substrate. A via is then etched in the dielectric layer to provide access to the substrate device and filled with copper or tungsten. A layer of a conducting metallic oxide is then deposited on the conducting plug, and a layer of ferroelectric material is deposited on the layer of conducting metal oxide. The layer of conducting metallic oxide is deposited at a temperature below 450° C., preferably at room temperature.
摘要翻译：一种电路元件，包括连接到衬底器件的铁电体器件。电路元件通过在半导体衬底中制造衬底器件并在半导体衬底上沉积电介质层来构成。然后在电介质层中蚀刻通孔以提供对衬底器件的接近并填充有铜或钨。然后将一层导电金属氧化物沉积在导电插塞上，并且一层铁电材料沉积在导电金属氧化物层上。导电金属氧化物层在低于450℃的温度下沉积，优选在室温下沉积。

6. 发明授权

US06610549B1 Amorphous barrier layer in a ferroelectric memory cell 失效
标题翻译：铁电存储单元中的无定形阻挡层
公开(公告)号：US06610549B1
公开(公告)日：2003-08-26
申请号：US09709051
申请日：2000-11-10
申请人： Sanjeev Aggarwal , Ramamoorthy Ramesh
发明人： Sanjeev Aggarwal , Ramamoorthy Ramesh
IPC分类号： H01L218239
CPC分类号： H01L21/7687 , H01L27/11502 , H01L28/55 , H01L28/75
摘要： A ferroelectric cell, particularly one integrated on a silicon substrate, comprising an amorphous barrier layer interposed between the ferroelectric stack and the silicon. Preferably, the ferroelectric stack includes conductive metal oxide electrodes sandwiching the ferroelectric layer. The metal oxide may act as a templating layer to crystallographically orient the ferroelectric layer. Alternatively, the electrodes and ferroelectric layer may be polycrystalline. The amorphous barrier layer may be composed of an intermetallic alloy, such as Ti3Al, a metal-metalloid, such as Pd—Si, a combination of early and later transition metals, such as Ti—Ni, and other related compound metal systems, such as (Ti, Zr)—Be, that form amorphous metals.
摘要翻译：特别是集成在硅衬底上的铁电电池，包括介于铁电堆和硅之间的无定形阻挡层。优选地，铁电体层包括夹着铁电体层的导电金属氧化物电极。金属氧化物可以用作模板层以使铁电层晶体取向。或者，电极和铁电层可以是多晶的。无定形阻挡层可以由诸如Ti 3 Al的金属间合金，诸如Pd-Si的金属 - 准金属，诸如Ti-Ni的早期和稍后的过渡金属的组合以及其它相关的复合金属体系组成，例如作为（Ti，Zr）-Be，形成无定形金属。

7. 发明授权

US6115281A Methods and structures to cure the effects of hydrogen annealing on ferroelectric capacitors 失效
标题翻译：固化氢退火对铁电电容器的影响的方法和结构
公开(公告)号：US6115281A
公开(公告)日：2000-09-05
申请号：US151903
申请日：1998-09-11
申请人： Sanjeev Aggarwal , Scott Robert Perusse , Ramamoorthy Ramesh
发明人： Sanjeev Aggarwal , Scott Robert Perusse , Ramamoorthy Ramesh
IPC分类号： H01L21/02 , H04L12/26 , H04L12/56 , H04Q11/04 , G11C11/22
CPC分类号： H04Q11/0478 , H01L28/55 , H01L28/75 , H04L49/3081 , H04L2012/5636
摘要： A ferroelectric memory cell integrated with silicon circuitry which require a forming-gas anneal of the silicon circuitry after the ferroelectric stack has been formed. The ferroelectric layer may have a composition such that there is no space in the lattice of the ferroelectric phase to accommodate atomic hydrogen or have a composition with a Curie temperature below the temperature of the forming-gas anneal. Preferably, there is no upper platinum electrode, or it is deposited after the forming-gas anneal. A metal-oxide upper electrode serves as barrier to the forming-gas anneal, and an intermetallic layer positioned above the ferroelectric stack serves as an even better barrier. Forming-gas damage to the ferroelectric stack can be removed by a recovery anneal in a hydrogen-free environment, preferably performed at a temperature above the Curie temperature.
摘要翻译：与硅电路集成的铁电存储单元，其在形成铁电叠层之后需要硅电路的成形气体退火。铁电层可以具有使铁电相的晶格中没有空间以适应原子氢或具有低于成形气体退火温度的居里温度的组成的组成。优选地，不存在上铂电极，或者在成形气体退火之后沉积。金属氧化物上电极用作形成气体退火的阻挡层，并且位于铁电堆叠上方的金属间层用作更好的屏障。铁电堆的形成气体损伤可以通过在无氢环境中的回收退火来去除，优选在高于居里温度的温度下进行。

8. 发明授权

US09356224B2 Thin film bismuth iron oxides useful for piezoelectric devices 有权
标题翻译：用于压电元件的薄膜铋铁氧化物
公开(公告)号：US09356224B2
公开(公告)日：2016-05-31
申请号：US12916209
申请日：2010-10-29
申请人： Robert J. Zeches , Lane W. Martin , Ramamoorthy Ramesh
发明人： Robert J. Zeches , Lane W. Martin , Ramamoorthy Ramesh
IPC分类号： H01L41/187 , H01L41/08 , H03H9/02 , H01L41/316
CPC分类号： H01L41/081 , H01L41/1878 , H01L41/316 , H03H9/02543
摘要： The present invention provides for a composition comprising a thin film of BiFeO3 having a thickness ranging from 20 nm to 300 nm, a first electrode in contact with the BiFeO3 thin film, and a second electrode in contact with the BiFeO3 thin film; wherein the first and second electrodes are in electrical communication. The composition is free or essentially free of lead (Pb). The BFO thin film is has the piezoelectric property of changing its volume and/or shape when an electric field is applied to the BFO thin film.
摘要翻译：本发明提供一种组合物，其包含厚度范围为20nm至300nm的BiFeO 3薄膜，与BiFeO 3薄膜接触的第一电极和与BiFeO 3薄膜接触的第二电极; 其中所述第一和第二电极是电连通的。组合物是游离的或基本上不含铅（Pb）。当向BFO薄膜施加电场时，BFO薄膜具有改变其体积和/或形状的压电特性。

9. 发明申请

US20110133601A1 Thin Film Bismuth Iron Oxides Useful for Piezoelectric Devices 有权
标题翻译：用于压电元件的薄膜铋铁氧化物
公开(公告)号：US20110133601A1
公开(公告)日：2011-06-09
申请号：US12916209
申请日：2010-10-29
申请人： Robert J. Zeches , Lane W. Martin , Ramamoorthy Ramesh
发明人： Robert J. Zeches , Lane W. Martin , Ramamoorthy Ramesh
IPC分类号： H01L41/02 , H01L41/00 , H01L41/24
CPC分类号： H01L41/081 , H01L41/1878 , H01L41/316 , H03H9/02543
摘要： The present invention provides for a composition comprising a thin film of BiFeO3 having a thickness ranging from 20 nm to 300 nm, a first electrode in contact with the BiFeO3 thin film, and a second electrode in contact with the BiFeO3 thin film; wherein the first and second electrodes are in electrical communication. The composition is free or essentially free of lead (Pb). The BFO thin film is has the piezoelectric property of changing its volume and/or shape when an electric field is applied to the BFO thin film.
摘要翻译：本发明提供一种组合物，其包含厚度范围为20nm至300nm的BiFeO 3薄膜，与BiFeO 3薄膜接触的第一电极和与BiFeO 3薄膜接触的第二电极; 其中所述第一和第二电极是电连通的。组合物是游离的或基本上不含铅（Pb）。当向BFO薄膜施加电场时，BFO薄膜具有改变其体积和/或形状的压电特性。

10. 发明授权

US06781176B2 Conductively doped strontium titanate barrier intermediate a silicon underlayer and an epitaxial metal oxide film 失效
标题翻译：在硅衬底和外延金属氧化物膜之间的导电掺杂的钛酸锶屏障
公开(公告)号：US06781176B2
公开(公告)日：2004-08-24
申请号：US10328541
申请日：2002-12-23
申请人： Ramamoorthy Ramesh
发明人： Ramamoorthy Ramesh
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , G11C11/22 , H01L21/28568 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： A ferroelectric memory cell formed on a monocrystalline silicon underlayer, either an epitaxial silicon contact plug to a transistor source or drain or silicon gate region for which the memory cell forms a non-volatile gate. A conductive barrier layer of vanadium or niobium substituted strontium titanate is epitaxially grown over the silicon, and a lower metal oxide electrode layer, a ferroelectric layer and an upper metal oxide electrode layer are epitaxially grown on the barrier layer. No platinum barrier is needed beneath the ferroelectric stack. The invention can be applied to many other functional oxide devices including micromachined electromechanical (MEM) devices and ferromagnetic tri-layer devices.
摘要翻译：在单晶硅衬底上形成的铁电存储单元，即存储单元形成非易失性栅极的硅晶体管源极或漏极或硅栅极区域的外延硅接触插塞。在硅上外延生长钒或铌取代钛酸锶的导电阻挡层，并且在阻挡层上外延生长下部金属氧化物电极层，铁电体层和上部金属氧化物电极层。铁电堆下方不需要铂金屏障。本发明可以应用于包括微加工机电（MEM）器件和铁磁性三层器件的许多其它功能氧化物器件。

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