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    • 1. 发明授权
    • Dense nanoscale logic circuitry
    • 密集的纳米级逻辑电路
    • US08390323B2
    • 2013-03-05
    • US13256234
    • 2009-04-30
    • Dmitri Borisovich StrukovPhilip J. Kuekes
    • Dmitri Borisovich StrukovPhilip J. Kuekes
    • H03K19/177
    • H01L27/24B82Y10/00
    • One embodiment of the present invention is directed to hybrid-nanoscale/microscale device comprising a microscale layer that includes microscale and/or submicroscale circuit components and that provides an array of microscale or submicroscale pins across an interface surface; and at least two nanoscale-layer sub-layers within a nanoscale layer that interfaces to the microscale layer, each nanoscale-layer sub-layer containing regularly spaced, parallel nanowires, each nanowire of the at least two nanoscale-layer sub-layers in electrical contact with at most one pin provided by the microscale layer, the parallel nanowires of successive nanoscale-layer sub-layers having different directions, with the nanowires of successive nanoscale-layer sub-layers intersecting to form programmable crosspoints.
    • 本发明的一个实施方案涉及包含微尺度层的混合纳米尺度/微米级器件,所述微米级层包括微米级和/或亚微米级电路部件,并且通过界面表面提供微米级或亚微米级引脚阵列; 以及在纳米尺度层内与微米级层相接触的至少两个纳米层子层,每个纳米级层子层含有规则间隔的平行纳米线,所述至少两个纳米级子层的每个纳米线在电 与由微尺度层提供的至多一个引脚接触,具有不同方向的连续纳米级子层的平行纳米线与连续的纳米级层子层的纳米线相交以形成可编程的交叉点。
    • 2. 发明申请
    • Dense Nanoscale Logic Circuitry
    • 密集的纳米级逻辑电路
    • US20120001653A1
    • 2012-01-05
    • US13256234
    • 2009-04-30
    • Dmitri Borisovich StrukovPhilip J. Kuekes
    • Dmitri Borisovich StrukovPhilip J. Kuekes
    • H03K19/173B82Y99/00
    • H01L27/24B82Y10/00
    • One embodiment of the present invention is directed to hybrid-nanoscale/microscale device comprising a microscale layer that includes microscale and/or submicroscale circuit components and that provides an array of microscale or submicroscale pins across an interface surface; and at least two nanoscale-layer sub-layers within a nanoscale layer that interfaces to the microscale layer, each nanoscale-layer sub-layer containing regularly spaced, parallel nanowires, each nanowire of the at least two nanoscale-layer sub-layers in electrical contact with at most one pin provided by the microscale layer, the parallel nanowires of successive nanoscale-layer sub-layers having different directions, with the nanowires of successive nanoscale-layer sub-layers intersecting to form programmable crosspoints.
    • 本发明的一个实施方案涉及包含微尺度层的混合纳米尺度/微米级器件,所述微米级层包括微米级和/或亚微米级电路部件,并且通过界面表面提供微米级或亚微米级引脚阵列; 以及在纳米尺度层内与微米级层相接触的至少两个纳米层子层,每个纳米级层子层含有规则间隔的平行纳米线,所述至少两个纳米级子层的每个纳米线在电 与由微尺度层提供的至多一个引脚接触,具有不同方向的连续纳米级子层的平行纳米线与连续的纳米级层子层的纳米线相交以形成可编程的交叉点。
    • 4. 发明授权
    • Scalable, component-accessible, and highly interconnected three-dimensional component arrangement within a system
    • 系统内可扩展的,可组件访问的和高度互连的三维组件布置
    • US08214786B2
    • 2012-07-03
    • US10935845
    • 2004-09-08
    • Philip J. KuekesR. Stanley WilliamsRaymond G. Beausoleil, Jr.
    • Philip J. KuekesR. Stanley WilliamsRaymond G. Beausoleil, Jr.
    • G06F17/50
    • G06F1/18G06F17/509H05K7/1444
    • Embodiments of the present invention include dense, but accessible and well-interconnected component arrangements within multi-component systems, such as high-end multi-processor computer systems, and methods for constructing such arrangements. In a described embodiment, integrated-circuit-containing processing components, referred to as a “flat components,” are arranged into local blocks of intercommunicating flat components. The local flat-component blocks are arranged into interconnected, primitive multi-local-block repeating units, and the primitive local-block repeating units are layered together in a three-dimensional, regularly repeating structure that can be assembled to approximately fill any specified three-dimensional volume. The arrangement provides for relatively short, direct pathways from the surface of the specified volume to any particular local block and flat component within the three-dimensional arrangement.
    • 本发明的实施例包括在诸如高端多处理器计算机系统的多组件系统内的密集但可访问和良好互连的组件布置,以及用于构造这种布置的方法。 在所描述的实施例中,被称为“平面部件”的集成电路的处理部件被布置在相互连通的平面部件的局部块中。 本地平面组件块被布置成互连的原始多局部块重复单元,并且原始局部块重复单元以三维的规则重复的结构分层在一起,其可以被组装以大致填充任何指定的三 维数。 该装置提供从指定体积的表面到三维布置中的任何特定局部块和平坦部件的相对短的直接通路。
    • 5. 发明申请
    • ANALOG TO DIGITAL CONVERTER
    • 模拟到数字转换器
    • US20120105263A1
    • 2012-05-03
    • US12916376
    • 2010-10-29
    • John Paul StrachanPhilip J. Kuekes
    • John Paul StrachanPhilip J. Kuekes
    • H03M1/12H05K3/00H05K1/09
    • H03M1/368Y10T29/49117
    • An analog to digital converter includes a dielectric substrate, an analog input wire, and digital output wires, with a metal insulator extending over the digital output wires. The analog input wire can be in proximity to the dielectric substrate and can generate heat when an electric current flows through the analog input wire. The digital output wires can also be in proximity to the dielectric substrate. The metal insulator can have a phase transition temperature above which the metal insulator is electrically conductive to short circuit at least one of the digital output wires in contact with a metal insulator portion above the phase transition temperature. The digital output wires can be arranged at predetermined distances from the analog input wire such that output wires have varying short circuit thresholds.
    • 模数转换器包括电介质基板,模拟输入线和数字输出线,金属绝缘体延伸在数字输出线上。 模拟输入线可以靠近电介质基板,并且当电流流过模拟输入线时可以产生热量。 数字输出线也可以靠近电介质基片。 金属绝缘体可以具有相对转变温度,在该相转变温度以上,金属绝缘体导电以使与数字输出线中至少一个与相变温度以上的金属绝缘体部分接触的短路。 数字输出线可以布置在距离模拟输入线的预定距离处,使得输出线具有变化的短路阈值。
    • 7. 发明授权
    • Sub-diffraction-limited imaging systems and methods
    • 次衍射限制成像系统和方法
    • US08045253B2
    • 2011-10-25
    • US12473402
    • 2009-05-28
    • Jingjing LiPhilip J. Kuekes
    • Jingjing LiPhilip J. Kuekes
    • G02F1/03G02F1/29G02B5/18
    • G02B27/56G01D5/30G02F1/29G02F2202/027G02F2202/20G02F2202/30G02F2202/36
    • Various embodiments of the present invention are directed to systems and methods for obtaining images of objects with higher resolution than the diffraction limit. In one aspect, a method for collecting evanescent waves scattered from an object comprises electronically configuring a reconfigurable device to operate as a grating for one or more lattice periods using a computing device. Propagating waves scattered from the object pass through the reconfigurable device and a portion of evanescent waves scattered from the object are projected into the far field of the object. The method includes detecting propagating waves and detecting the portion of evanescent waves projected into the far field for each lattice period using an imaging system.
    • 本发明的各种实施例涉及用于获得具有比衍射极限更高分辨率的物体的图像的系统和方法。 一方面,一种用于收集从物体散射的ev逝波的方法包括使用计算装置电子地配置可重构装置作为一个或多个晶格周期的光栅。 从物体散射的传播波通过可重构装置,并且从物体散射的一部分ev逝波被投射到物体的远场中。 该方法包括使用成像系统检测传播波并且检测投射到远场中的每个格周期的瞬逝波的部分。