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    • 2. 发明授权
    • In-situ nitridation of high-k dielectrics
    • 高k电介质的原位氮化
    • US07704821B2
    • 2010-04-27
    • US11146826
    • 2005-06-07
    • Dina H. TriyosoOlubunmi O. AdetutuHsing H. Tseng
    • Dina H. TriyosoOlubunmi O. AdetutuHsing H. Tseng
    • H01L21/8238
    • H01L29/517H01L21/28194H01L21/28202H01L21/28229H01L29/513H01L29/518H01L29/78
    • A semiconductor fabrication process for forming a gate dielectric includes depositing a high-k dielectric stack including incorporating nitrogen into the high-k dielectric stack in-situ. A top high-k dielectric is formed overlying the dielectric stack and the dielectric stack and the top dielectric are annealed. Depositing the dielectric stack includes depositing a plurality of high-k dielectric layers where each layer is formed in a distinct processing step or set of steps. Depositing one of the dielectric layers includes performing a plurality of atomic layer deposition processes to form a plurality of high-k sublayers, wherein each sublayer is a monolayer film. Depositing the plurality of sublayers includes depositing a nitrogen free sublayer and depositing a nitrogen bearing sublayer. Depositing the nitrogen free sublayer includes pulsing an ALD chamber with HfCl4, purging the chamber with an inert, pulsing the chamber with an H2O or D2O, and purging the chamber with an inert.
    • 用于形成栅极电介质的半导体制造工艺包括沉积高k电介质堆叠,其包括将氮掺杂到原位的高k电介质堆叠中。 形成覆盖在电介质堆叠上的顶部高k电介质,并且电介质堆叠和顶部电介质被退火。 沉积介电堆叠包括沉积多个高k电介质层,其中每个层以不同的处理步骤或一组步骤形成。 沉积一个电介质层包括执行多个原子层沉积工艺以形成多个高k子层,其中每个子层是单层膜。 沉积多个子层包括沉积无氮的子层并沉积含氮的子层。 沉积无氮子层包括用HfCl 4脉冲ALD室,用惰性气体冲洗室,用H 2 O或D 2 O脉冲室,并用惰性气体清洗室。
    • 7. 发明授权
    • Transitional dielectric layer to improve reliability and performance of high dielectric constant transistors
    • 过渡介电层提高高介电常数晶体管的可靠性和性能
    • US07235502B2
    • 2007-06-26
    • US11096515
    • 2005-03-31
    • Sriram S. KalpatVoon-Yew TheanHsing H. TsengOlubunmi O. Adetutu
    • Sriram S. KalpatVoon-Yew TheanHsing H. TsengOlubunmi O. Adetutu
    • H01L21/31
    • H01L21/022H01L21/02175H01L21/0228H01L21/28194H01L21/3141H01L29/513H01L29/517
    • A gate dielectric structure (201) fabrication process includes forming a transitional dielectric film (205) overlying a silicon oxide film (204). A high dielectric constant film (206) is then formed overlying an upper surface of the transitional dielectric film (205). The composition of the transitional dielectric film (205) at the silicon oxide film (204) interface primarily comprises silicon and oxygen. The high K dielectric (206) and the composition of the transitional dielectric film (205) near the upper surface primarily comprise a metal element and oxygen. Forming the transitional dielectric film (205) may include forming a plurality of transitional dielectric layers (207) where the composition of each successive transitional dielectric layer (207) has a higher concentration of the metal element and a lower concentration of silicon. Forming the transitional dielectric layer (205) may include performing multiple cycles of an atomic layer deposition process (500) where a precursor concentration for each cycle differs from the precursor concentration of the preceding cycle.
    • 栅极电介质结构(201)制造工艺包括形成覆盖氧化硅膜(204)的过渡电介质膜(205)。 然后形成覆盖在过渡介电膜(205)的上表面上的高介电常数膜(206)。 氧化硅膜(204)界面处的过渡电介质膜(205)的组成主要包括硅和氧。 高K电介质(206)和上表面附近的过渡电介质膜(205)的组成主要包括金属元素和氧。 形成过渡电介质膜(205)可以包括形成多个过渡介电层(207),其中每个连续的过渡介电层(207)的组成具有较高的金属元素浓度和较低的硅浓度。 形成过渡电介质层(205)可以包括执行原子层沉积工艺(500)的多个循环,其中每个循环的前体浓度与先前循环的前体浓度不同。
    • 10. 发明授权
    • Method of forming an electronic device
    • 电子设备的形成方法
    • US07214590B2
    • 2007-05-08
    • US11098874
    • 2005-04-05
    • Sangwoo LimPaul A. GrudowskiMohamad M. JahanbaniHsing H. TsengChoh-Fei Yeap
    • Sangwoo LimPaul A. GrudowskiMohamad M. JahanbaniHsing H. TsengChoh-Fei Yeap
    • H01L21/336
    • H01L21/823462
    • A method of forming an electronic device includes etching a portion of a first gate dielectric layer to reduce a thickness of the gate dielectric layer within that portion. In one embodiment, portions not being etched may be covered by mask. In another embodiment, different portions may be etched during different times to give different thicknesses for the first gate dielectric layer. In a particular embodiment, a second gate dielectric layer may be formed over the first gate dielectric layer after etching the portion. The second gate dielectric layer can have a dielectric constant greater than the dielectric constant of the first gate dielectric layer. Subsequent gate electrode and source/drain region formation can be performed to form a transistor structure.
    • 形成电子器件的方法包括蚀刻第一栅极介电层的一部分以减小该部分内的栅极介电层的厚度。 在一个实施例中,未被蚀刻的部分可以被掩模覆盖。 在另一个实施例中,不同部分可以在不同时间被蚀刻,以给予第一栅极介电层不同的厚度。 在特定实施例中,可以在蚀刻该部分之后在第一栅极电介质层上形成第二栅极电介质层。 第二栅极介电层可以具有大于第一栅极介电层的介电常数的介电常数。 可以进行随后的栅电极和源/漏区形成以形成晶体管结构。