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    • 2. 发明授权
    • Air purge collar
    • 空气吹扫圈
    • US08931908B2
    • 2015-01-13
    • US12183647
    • 2008-07-31
    • Derek WilliamsGary GarnierKent StemerPaul Carlson
    • Derek WilliamsGary GarnierKent StemerPaul Carlson
    • B60R1/00F15D1/00
    • F15D1/00G01N2021/151Y10T137/0324Y10T137/2082Y10T137/2224
    • An air purge apparatus and method is presented to protect an imaging system from contamination by particulate matter and other substances in the ambient environment. The apparatus is adapted to be placed adjacent to a viewing window, lens or optics of an imaging system and to provide a protective flow of air. The apparatus includes a curved surface to direct air from a first plenum toward an imaging path in front of the apparatus. The apparatus also includes one or more openings nearer the lens to direct air from a second plenum into the imaging path. The air from the first plenum entrains air from the second plenum and ambient air to create a fluid stream away from the viewing window, lens, or optics and may form a fluid barrier to reduce contamination of a volume of air in the imaging path of the imaging sensor.
    • 提供了一种空气净化装置和方法,以保护成像系统免受周围环境中的颗粒物质和其他物质的污染。 该装置适于放置成与成像系统的观察窗,透镜或光学元件相邻并且提供保护性空气流。 该装置包括弯曲表面,用于将来自第一集气室的空气引向装置前面的成像路径。 该设备还包括靠近透镜的一个或多个开口以将空气从第二增压室引导到成像路径中。 来自第一增压室的空气带动来自第二增压室和环境空气的空气以产生远离观察窗,透镜或光学器件的流体流,并且可以形成流体屏障,以减少成像路径中的空气体积的污染 成像传感器。
    • 3. 发明申请
    • METHOD AND DATA PROCESSING SYSTEM FOR MICROPROCESSOR COMMUNICATION IN A CLUSTER-BASED MULTI-PROCESSOR SYSTEM
    • 基于群集多处理器系统的微处理器通信的方法和数据处理系统
    • US20080091918A1
    • 2008-04-17
    • US11952479
    • 2007-12-07
    • Ravi ArimilliRobert CargnoniDerek WilliamsKenneth Wright
    • Ravi ArimilliRobert CargnoniDerek WilliamsKenneth Wright
    • G06F15/76G06F9/02
    • H04L69/16G06F15/17H04L12/42H04L67/1002H04L69/161H04W28/14
    • A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
    • 包含在多处理器集群系统内的处理器通信寄存器(PCR)提供增强的处理器通信。 PCR存储在流水线或并行多处理中有用的信息。 每个处理器集群具有存储到PCR中的扇区的独占权限,并且具有连续访问以读取其内容。 每个处理器集群在PCR中更新其独占部分,立即允许集群网络内的所有其他处理器查看PCR数据中的更改,并绕过缓存子系统。 处理器集群网络中的效率得到提高,通过提供处理器通信来立即联网并传输到所有处理器中,而不会立即限制对信息的访问,或迫使所有处理器持续竞争相同的高速缓存行,从而压倒互连和内存 系统具有无限的加载流,存储和无效命令。
    • 6. 发明申请
    • Method, system and program product for specifying a configuration for a digital system utilizing dial biasing weights
    • 用于指定利用拨盘偏置权重的数字系统的配置的方法,系统和程序产品
    • US20070180423A1
    • 2007-08-02
    • US11345847
    • 2006-02-02
    • Bryan HuntWolfgang RoesnerRobert ShadowenDerek Williams
    • Bryan HuntWolfgang RoesnerRobert ShadowenDerek Williams
    • G06F17/50
    • G06F17/5045
    • In a method of data processing, a database defines a Dial entity and at least one instance of the Dial entity. Each instance of the Dial entity has an input having a plurality of different possible input values and one or more outputs, and each of the plurality of different possible input values has a different associated output value set for the one or more outputs. Each instance of the Dial entity determines a value of at least one of a plurality of configuration latches in a digital system separate from the database. The database also associates with the Dial entity at least one set of biasing weights that, when applied, determines a probability of each instance of the Dial entity having particular ones of the plurality of different possible input values. In response to a call to set the plurality of configuration latches, the database is accessed to apply the at least one set of biasing weights to select one of the plurality of different possible input values for the at least one instance of the Dial entity. The plurality of configuration latches in the digital system are set based upon the output value set for the one or more outputs of the at least one instance of the Dial entity.
    • 在数据处理的方法中,数据库定义了Dial实体和Dial实体的至少一个实例。 Dial实体的每个实例具有具有多个不同可能输入值和一个或多个输出的输入,并且多个不同可能输入值中的每一个具有为一个或多个输出设置的不同的相关输出值。 Dial实体的每个实例确定与数据库分离的数字系统中的多个配置锁存器中的至少一个的值。 所述数据库还将所述至少一组偏置权重与所述拨号实体相关联,所述偏置权重在被应用时确定具有所述多个不同可能输入值中的特定个体的所述拨号实体的每个实例的概率。 响应于设置多个配置锁存器的呼叫,访问数据库以应用至少一组偏置权重以选择Dial实体的至少一个实例的多个不同可能输入值中的一个。 基于为Dial实体的至少一个实例的一个或多个输出设置的输出值来设置数字系统中的多个配置锁存器。
    • 7. 发明申请
    • Chained cache coherency states for sequential non-homogeneous access to a cache line with outstanding data response
    • 链接高速缓存一致性状态用于对具有出色数据响应的高速缓存行的顺序非均匀访问
    • US20070083716A1
    • 2007-04-12
    • US11245312
    • 2005-10-06
    • Ramakrishnan RajamonyHazim ShafiDerek WilliamsKenneth Wright
    • Ramakrishnan RajamonyHazim ShafiDerek WilliamsKenneth Wright
    • G06F13/28
    • G06F12/0831
    • A method for sequentially coupling successive processor requests for a cache line before the data is received in the cache of a first coupled processor. Both homogenous and non-homogenous operations are chained to each other, and the coherency protocol includes several new intermediate coherency responses associated with the chained states. Chained coherency states are assigned to track the chain of processor requests and the grant of access permission prior to receipt of the data at the first processor. The chained coherency states also identify the address of the receiving processor. When data is received at the cache of the first processor within the chain, the processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chained coherency protocol frees up address bus bandwidth by reducing the number of retries.
    • 一种用于在数据在第一耦合处理器的高速缓存中接收数据之前顺序耦合高速缓存行的连续处理器请求的方法。 同质和非均匀的操作彼此链接,并且一致性协议包括与链接状态相关联的几个新的中间一致性响应。 分配链接一致性状态以在第一处理器接收到数据之前跟踪处理器请求链和授予访问权限。 链接的一致性状态还标识接收处理器的地址。 当在链中的第一处理器的高速缓存处接收到数据时,处理器完成其对(或)数据的操作,然后将数据转发到链中的下一个处理器。 链接的一致性协议通过减少重试次数来释放地址总线带宽。
    • 9. 发明申请
    • Reducing number of rejected snoop requests by extending time to respond to snoop request
    • 通过延长响应窥探请求的时间来减少被拒绝的窥探请求数
    • US20060184746A1
    • 2006-08-17
    • US11056679
    • 2005-02-11
    • Guy GuthrieHugh ShenWilliam StarkeDerek Williams
    • Guy GuthrieHugh ShenWilliam StarkeDerek Williams
    • G06F13/28
    • G06F13/1605G06F12/0831
    • A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. The snoop request is entered in the first available latch of the stall/reorder unit unless the stall/reorder unit is full in which case the new snoop request is transmitted to a second unit configured to transmit a request to retry resending the new snoop request. Snoop requests have a higher priority than requests from processors and snoop requests are selected by the arbitration mechanism over processor requests unless the arbitration mechanism requests otherwise (“stall request”) to the stall/reorder unit. By snoop requests having a higher priority than processor requests, the number of snoop requests rejected is reduced. By having the arbitration mechanism issue a stall request, the processor will not be starved.
    • 用于减少拒绝的窥探请求数量的缓存,系统和方法。 缓存中的“停止/重新排序单元”从互连中接收窥探请求。 监听请求被输入到停止/重新排序单元的第一可用锁存器中,除非停止/重新排序单元已满,在这种情况下,新的窥探请求被发送到被配置为发送重新发送新的窥探请求的请求的第二单元。 侦听请求具有比来自处理器的请求更高的优先级,并且仲裁机制通过处理器请求选择侦听请求,除非仲裁机制另请求(“停止请求”)到停止/重新排序单元。 通过具有比处理器请求更高优先级的侦听请求,减少了被拒绝的侦听请求的数量。 通过使仲裁机制发出停顿请求,处理器不会饿死。