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1. 发明授权

US5798277A Method for fabricating heterojunction bipolar transistor 失效
标题翻译：异质结双极晶体管的制造方法
公开(公告)号：US5798277A
公开(公告)日：1998-08-25
申请号：US729841
申请日：1996-10-15
申请人： Byung-Ryul Ryum , Tae-Hyeon Han , Deok-Ho Cho , Soo-Min Lee , Kwang-Eui Pyun
发明人： Byung-Ryul Ryum , Tae-Hyeon Han , Deok-Ho Cho , Soo-Min Lee , Kwang-Eui Pyun
IPC分类号： H01L29/70 , H01L21/331 , H01L29/08 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/7371 , Y10S148/05 , Y10S148/072
摘要： An improved method for fabricating a heterojunction bipolar transistor which includes the steps of forming a buried collector, a collector thin film, and a collector sinker on a semiconductor substrate in order, forming a first silicon oxide film, a base electrode polysilicon layer, a nitride film, and an oxidation film on a resulting substrate exposing the first silicon oxidation film, forming a spacer insulation film at the lateral side of the exposed region, and defining an activation region, exposing the collector thin film of the activation region using a mask, and forming an auxiliary lateral film for an isolation of the device, forming a selective collector region by ion-implantating a dopant to the activation region which is limited by the auxiliary lateral film, removing the auxiliary lateral film, etching the exposed portion in an anisotropic etching method, and forming a shallow trench for a device isolation, forming a polysilicon lateral film to have a height which is the same as the height of the base electrode polysilicon layer on the shallow trench, and forming a self-aligned base.
摘要翻译：一种用于制造异质结双极晶体管的改进方法，其包括以下步骤：在半导体衬底上形成掩埋集电极，集电极薄膜和集电极沉降片，以形成第一氧化硅膜，基极多晶硅层，氮化物在所得到的基板上暴露第一硅氧化膜的氧化膜，在暴露区域的侧面形成间隔绝缘膜，并限定激活区域，使用掩模曝光激活区域的集电极薄膜，并形成用于隔离器件的辅助横向膜，通过将离子注入到由辅助侧膜限制的活化区域的掺杂剂形成选择性集电极区域，去除辅助横向膜，在各向异性层中蚀刻暴露部分蚀刻方法，以及形成用于器件隔离的浅沟槽，形成多晶硅侧膜以具有s的高度 ame作为浅沟槽上的基极多晶硅层的高度，并形成自对准基底。

2. 发明授权

US06190984B1 Method for fabricating of super self-aligned bipolar transistor 失效
标题翻译：超自对准双极晶体管的制造方法
公开(公告)号：US06190984B1
公开(公告)日：2001-02-20
申请号：US09229831
申请日：1999-01-13
申请人： Byung-Ryul Ryum , Deok-Ho Cho , Tae-Hyeon Han , Soo-Min Lee , Kwang-Eui Pyun
发明人： Byung-Ryul Ryum , Deok-Ho Cho , Tae-Hyeon Han , Soo-Min Lee , Kwang-Eui Pyun
IPC分类号： H01L218222
CPC分类号： H01L29/66242
摘要： The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.
摘要翻译：本发明涉及一种用于制造能够使元件小型化的超自对准异质结双极晶体管的方法，通过采用选择性集电体外延生长工艺简化其工艺步骤，而不使用用于元件间隔离的沟槽。根据本发明，通过使用限定发射极区域和第二间隔物的掩模来导出元件之间的隔离。基层具有由Si，未掺杂的SiGe，SiGe原位掺杂p型杂质的Si和Si构成的多层结构。此外，不需要基底的选择性外延生长。因此，可能不太容易发生漏电流或发射极 - 基极 - 集电极短路效应。

3. 发明授权

US5668022A Silicon-silicon-germanium heterojunction bipolar transistor fabrication method 失效
标题翻译：硅硅锗异质结双极晶体管制造方法
公开(公告)号：US5668022A
公开(公告)日：1997-09-16
申请号：US700930
申请日：1996-08-23
申请人： Deok-Ho Cho , Soo-Min Lee , Tae-Hyeon Han , Byung-Ryul Ryum , Kwang-Eui Pyun
发明人： Deok-Ho Cho , Soo-Min Lee , Tae-Hyeon Han , Byung-Ryul Ryum , Kwang-Eui Pyun
IPC分类号： H01L29/73 , H01L21/331 , H01L29/165 , H01L29/732 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66242 , H01L29/7378 , Y10S148/072
摘要： A silicon/silicon-germanium bipolar transistor fabrication method employs a metallic silicide film as an extrinsic base electrode to reduce resistance of the extrinsic base electrode, and to increase a maximum oscillation frequency and cut-off frequency due to its self-aligned structure. The fabrication method enables agglomeration to occur on the side wall of the polycrystalline silicon film connected to the metallic silicide film instead of on the interface between the metallic silicide film and the lower silicon/silicon-germanium film, and leads the extrinsic base electrode to be sandwitched by the insulator films, thereby realizing a constant resistance and also resulting in the application of integrated circuits to a mass production mechanism.
摘要翻译：硅/硅 - 锗双极晶体管制造方法使用金属硅化物膜作为外部基极，以降低外部基极的电阻，并且由于其自对准结构而增加最大振荡频率和截止频率。该制造方法可以在连接到金属硅化物膜的多晶硅膜的侧壁上而不是在金属硅化物膜和下硅/硅 - 锗膜之间的界面上发生聚集，并且引导外部基极为由绝缘体膜切割，从而实现恒定的电阻，并且还导致集成电路应用于大规模生产机构。

4. 发明授权

US5962879A Super self-aligned bipolar transistor 失效
标题翻译：超自对准双极晶体管
公开(公告)号：US5962879A
公开(公告)日：1999-10-05
申请号：US854665
申请日：1997-05-12
申请人： Byung-Ryul Ryum , Deok-Ho Cho , Tae-Hyeon Han , Soo-Min Lee , Kwang-Eui Pyun
发明人： Byung-Ryul Ryum , Deok-Ho Cho , Tae-Hyeon Han , Soo-Min Lee , Kwang-Eui Pyun
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/7378
摘要： The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.
摘要翻译：本发明涉及一种用于制造能够使元件小型化的超自对准异质结双极晶体管的方法，通过采用选择性集电体外延生长工艺简化其工艺步骤，而不使用用于元件间隔离的沟槽。根据本发明，通过使用限定发射极区域和第二间隔物的掩模来导出元件之间的隔离。基层具有由Si，未掺杂的SiGe，SiGe原位掺杂p型杂质的Si和Si构成的多层结构。此外，不需要基底的选择性外延生长。因此，可能不太容易发生漏电流或发射极 - 基极 - 集电极短路效应。

5. 发明授权

US5696007A Method for manufacturing a super self-aligned bipolar transistor 失效
标题翻译：用于制造超自对准双极晶体管的方法
公开(公告)号：US5696007A
公开(公告)日：1997-12-09
申请号：US729840
申请日：1996-10-15
申请人： Byung-Ryul Ryum , Tae-Hyeon Han , Deok-Ho Cho , Soo-Min Lee , Kwang-Eui Pyun
发明人： Byung-Ryul Ryum , Tae-Hyeon Han , Deok-Ho Cho , Soo-Min Lee , Kwang-Eui Pyun
IPC分类号： H01L29/73 , H01L21/331 , H01L29/165 , H01L29/70 , H01L29/732 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66242 , H01L29/7378 , Y10S148/072
摘要： The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth and a polycide base electrode without using a trench for isolating between elements, thereby enhancing the performance thereof, which comprises the steps of: forming sequently a first oxidation film, an electrically conducting thin film and a second oxidation film on top of a substrate; patterning the second oxidation film and the conducting thin film to form a preliminary spacer; removing an exposed portion of the first oxidation film, and selectively growing a collector layer; oxidizing the collector layer to form a thermal oxidation film, and removing the preliminary spacer; depositing a polysilicon and forming a silicon oxidation film and a polysilicon spacer on the second oxidation film and the removed portion of the preliminary spacer, respectively; exposing the base thin film, the spacer and the collector layer to form a SiGe/Si layer; forming a base electrode on the SiGe/Si layer; exposing a portion of the first oxidation film and forming a third oxidation film; exposing a surface of the SiGe/Si layer and forming a oxidation spacer on sides of an etched portion, then self-aligning the emitter and the emitter electrode; and performing a metal wiring process.
摘要翻译：本发明涉及一种能够使元件小型化的超自对准异质结双极晶体管的制造方法，通过采用选择性集电体外延生长和多选择性基极电极简化其工艺步骤，而不使用用于隔离元件之间的沟槽，从而提高其性能，其包括以下步骤：在衬底的顶部上顺次形成第一氧化膜，导电薄膜和第二氧化膜; 图案化第二氧化膜和导电薄膜以形成预备间隔物; 去除第一氧化膜的暴露部分，并选择性地生长集电体层; 氧化所述集电体层以形成热氧化膜，并除去所述预备间隔物; 在所述第二氧化膜上分别沉积多晶硅并形成硅氧化膜和多晶硅间隔物和所述预备间隔物的去除部分; 暴露基底薄膜，间隔物和集电极层以形成SiGe / Si层; 在SiGe / Si层上形成基极; 暴露第一氧化膜的一部分并形成第三氧化膜; 暴露SiGe / Si层的表面并在蚀刻部分的侧面上形成氧化间隔物，然后自发对准发射极和发射极; 并执行金属布线处理。

6. 发明授权

US5895930A Infrared photodetector with doping superlattice structure 失效
标题翻译：具有掺杂超晶格结构的红外光电探测器
公开(公告)号：US5895930A
公开(公告)日：1999-04-20
申请号：US891495
申请日：1997-07-11
申请人： Eung-Gie Oh , Jeon-Wook Yang , Chul-Soon Park , Kwang-Eui Pyun
发明人： Eung-Gie Oh , Jeon-Wook Yang , Chul-Soon Park , Kwang-Eui Pyun
IPC分类号： H01L31/09 , H01L31/0352 , H01L29/06
CPC分类号： B82Y20/00 , H01L31/035236
摘要： This invention provides infrared sensing photodetector and a method therefor which provides a structure for effectively absorbing a light incident in a normal direction on a substrate, and a method compatible with existing processes for making integrated circuitry. An infrared sensing photodetector includes a compound semiconductor substrate of a first conductivity type, superlattice areas having implanted impurity ions of a second conductivity type opposite to the compound semiconductor substrate, each being spaced a predetermined distance each other in a selected region of the semiconductor substrate, a first collector area and a first emitter area which are formed in both end portions positioned perpendicular relative to the doped superlattice areas, a first collector electrode and a first emitter electrode formed on the first collector area and the first emitter area, respectively, a second collector area and a second emitter area which are spaced a predetermined distance in a horizontal direction on the doped superlattice area, and a second collector electrode and a second emitter electrode formed on the second collector area and the second emitter area, respectively.
摘要翻译：本发明提供了一种红外感测光电检测器及其方法，其提供了用于有效吸收在基板上沿正向入射的光的结构，以及与用于制造集成电路的现有工艺兼容的方法。红外感测光电检测器包括具有第一导电类型的化合物半导体衬底，具有注入的与化合物半导体衬底相反的第二导电类型的杂质离子的超晶格区域，在半导体衬底的选定区域中彼此隔开预定距离，第一集电极区域和第一发射极区域，其形成在相对于掺杂的超晶格区域垂直定位的两个端部中，第一集电极电极和第一发射极电极分别形成在第一集电区域和第一发射极区域上，集电极区域和在掺杂超晶格区域上在水平方向上隔开预定距离的第二发射极区域，以及分别形成在第二集电极区域和第二发射极区域上的第二集电极电极和第二发射极电极。

7. 发明授权

US5861327A Fabrication method of gate electrode in semiconductor device 失效
标题翻译：半导体器件中栅电极的制造方法
公开(公告)号：US5861327A
公开(公告)日：1999-01-19
申请号：US889939
申请日：1997-07-10
申请人： Sung-Jae Maeng , Jae-Jin Lee , Kwang-Eui Pyun
发明人： Sung-Jae Maeng , Jae-Jin Lee , Kwang-Eui Pyun
IPC分类号： H01L21/336 , H01L21/027 , H01L21/285 , H01L21/338
CPC分类号： H01L29/66863 , H01L21/0274 , H01L21/28581 , H01L21/28587
摘要： A fabrication method of a semiconductor device is disclosed. A T-shaped gate used for decreasing the gate resistance is adopted in fabricating an ultrahigh frequency and low-noise device. According to the present invention, a gate pattern is formed by a dual exposure technique, a thin metal film is formed, a pattern for plating is formed, and a gate is formed by electroplating, whereby decreasing a gate length and gate resistance. Therefore, the cost of production is decreased, the yield is improved, and the noise figure is minimized.
摘要翻译：公开了一种半导体器件的制造方法。在制造超高频和低噪声器件时采用了用于降低栅极电阻的T形栅极。根据本发明，通过双重曝光技术形成栅极图案，形成薄金属膜，形成用于电镀的图案，并且通过电镀形成栅极，从而减小栅极长度和栅极电阻。因此，生产成本降低，产量提高，噪音指标最小化。

8. 发明授权

US5702975A Method for isolating semiconductor device 失效
标题翻译：隔离半导体器件的方法
公开(公告)号：US5702975A
公开(公告)日：1997-12-30
申请号：US719876
申请日：1996-09-25
申请人： Hyung-Sup Yoon , Jin-Hee Lee , Chul-Sun Park , Kwang-Eui Pyun
发明人： Hyung-Sup Yoon , Jin-Hee Lee , Chul-Sun Park , Kwang-Eui Pyun
IPC分类号： H01L29/40 , H01L21/285 , H01L21/335 , H01L21/76 , H01L21/302
CPC分类号： H01L29/66462 , H01L21/28587 , H01L21/7605
摘要： A method for isolating a semiconductor device is disclosed including the steps of sequentially growing a plurality of material layers on a semiconductor substrate, etching the material layers down to a predetermined depth of the substrate to thereby define an active region, forming a semi-insulating film on the exposed semiconductor substrate in order to planarize the step-difference of the active region and the isolation region, and then, forming an ohmic metal layer on a space where the semi-insulating film is regrown.
摘要翻译：公开了一种用于隔离半导体器件的方法，包括以下步骤：在半导体衬底上顺序生长多个材料层，将材料层蚀刻到衬底的预定深度，从而限定有源区，形成半绝缘膜在露出的半导体衬底上，以平坦化有源区和隔离区的阶梯差，然后在再次生长半绝缘膜的空间上形成欧姆金属层。

9. 发明授权

US5496779A Method for fabricating a self-aligned T-gate metal semiconductor field effect transistor 失效
标题翻译：制造自对准T型栅极金属半导体场效应晶体管的方法
公开(公告)号：US5496779A
公开(公告)日：1996-03-05
申请号：US358886
申请日：1994-12-19
申请人： Kyung-Ho Lee , Youn-Kyu Bae , Kwang-Eui Pyun , Kyung-Soo Kim
发明人： Kyung-Ho Lee , Youn-Kyu Bae , Kwang-Eui Pyun , Kyung-Soo Kim
IPC分类号： H01L29/812 , H01L21/285 , H01L21/335 , H01L21/338 , H01L21/265
CPC分类号： H01L29/66878 , H01L21/28587
摘要： Disclosed is a method of fabricating a metal semiconductor field effect transistor, comprising the steps for, forming the channel using an ion-implantation, sequentially forming a first insulator layer at a first predetermined temperature and a second insulation layer at second predetermined temperature over the surface of the substrate, etching the first and second insulation layers using a gate pattern of a photo-resist pattern to expose the channel region as a mask, forming a refractory metal over the surface of the first and second insulation layer add the exposed channel region, etching the refractory metal, thereby dividing it into two parts of which one is formed on the channel region and the other is formed on the second insulation layer, selectively etching the first and second insulation layers to lift-off the refractory metal over the first and second insulation layers, thereby forming a gate of a T-shape on the channel region, ion implanting Si into a substrate using the gate and a channel pattern of a photo-resist film to form a self-aligned high concentration ion implantation region, forming a third insulation layer for preventing As of evaporation, carrying out a rapid thermal annealing for activation, removing the third insulation layer; and forming an ohmic electrode using a lift-off process.
摘要翻译：公开了一种制造金属半导体场效应晶体管的方法，包括以下步骤：使用离子注入形成沟道，顺序地形成第一预定温度的第一绝缘体层和在表面上的第二预定温度的第二绝缘层使用光致抗蚀剂图案的栅极图案蚀刻第一绝缘层和第二绝缘层以暴露沟道区域作为掩模，在第一和第二绝缘层的表面上形成耐火金属添加暴露的沟道区，蚀刻耐火金属，从而将其分成两部分，其中一部分形成在沟道区上，另一部分形成在第二绝缘层上，选择性地蚀刻第一绝缘层和第二绝缘层以在第一绝缘层上剥离难熔金属，第二绝缘层，从而在沟道区上形成T形栅极，使用ga将Si离子注入衬底和形成自对准高浓度离子注入区的通道图案，形成用于防止As蒸发的第三绝缘层，进行激活的快速热退火，去除第三绝缘层; 并使用剥离工艺形成欧姆电极。

10. 发明授权

US5970328A Fabrication method of T-shaped gate electrode in semiconductor device 失效
标题翻译：半导体器件中T形栅电极的制作方法
公开(公告)号：US5970328A
公开(公告)日：1999-10-19
申请号：US961407
申请日：1997-10-30
申请人： Byung-Sun Park , Jin-Hee Lee , Hyung-Sup Yoon , Chul-Sun Park , Kwang-Eui Pyun
发明人： Byung-Sun Park , Jin-Hee Lee , Hyung-Sup Yoon , Chul-Sun Park , Kwang-Eui Pyun
IPC分类号： H01L21/28 , H01L21/285 , H01L21/335 , H01L29/423 , H01L21/338
CPC分类号： H01L29/66462 , H01L21/28581 , H01L21/28587 , H01L29/42316
摘要： A method for fabricating a T-shaped gate electrode of a high speed semiconductor device such as HEMTs which is applied to high speed logic circuit including low-noise receivers and power amplifiers having a frequency of X-band or more respectively, and MMICs having a frequency of millimeter wave band. Such devices require a short gate length and a large sectional area of the gate pattern. The conventional photolithography techniques are in need of the resolution for fabricating a fine line width. Therefore, electron-beam lithography is most widely used. But, it is difficult to enhance throughput in manufacturing semiconductor devices because a lot of exposure time is required in the methods using electron beams. In the present invention, a silicon oxide film or a silicon nitride film is deposited on a mono-layered resist pattern. A dummy pattern corresponding to a leg of the gate is formed using the silicon oxide film or the silicon nitride film. A leg of the gate electrode is formed at the portion of the dummy pattern. According to the present invention, a step for improving the resolution is not required, and a gate electrode having a very fine line width of a few hundreds .ANG. can be obtained by regulating the thickness of the silicon nitride film.
摘要翻译：一种用于制造诸如HEMT的高速半导体器件的T形栅极的方法，其应用于包括具有X频带或更多频率的低噪声接收机和功率放大器的高速逻辑电路，以及具有毫米波段的频率。这样的器件需要栅极长度短和栅极图案的大截面积。常规的光刻技术需要用于制造细线宽度的分辨率。因此，电子束光刻被广泛使用。但是，由于在使用电子束的方法中需要大量的曝光时间，所以难以提高制造半导体器件的吞吐量。在本发明中，在单层抗蚀剂图案上沉积氧化硅膜或氮化硅膜。使用氧化硅膜或氮化硅膜形成对应于栅极支脚的虚拟图案。栅电极的一条腿形成在虚拟图案的部分。根据本发明，不需要提高分辨率的步骤，并且可以通过调节氮化硅膜的厚度来获得具有几百安培的极细线宽的栅电极。

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