专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5798277A Method for fabricating heterojunction bipolar transistor 失效
标题翻译：异质结双极晶体管的制造方法
公开(公告)号：US5798277A
公开(公告)日：1998-08-25
申请号：US729841
申请日：1996-10-15
申请人： Byung-Ryul Ryum , Tae-Hyeon Han , Deok-Ho Cho , Soo-Min Lee , Kwang-Eui Pyun
发明人： Byung-Ryul Ryum , Tae-Hyeon Han , Deok-Ho Cho , Soo-Min Lee , Kwang-Eui Pyun
IPC分类号： H01L29/70 , H01L21/331 , H01L29/08 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/7371 , Y10S148/05 , Y10S148/072
摘要： An improved method for fabricating a heterojunction bipolar transistor which includes the steps of forming a buried collector, a collector thin film, and a collector sinker on a semiconductor substrate in order, forming a first silicon oxide film, a base electrode polysilicon layer, a nitride film, and an oxidation film on a resulting substrate exposing the first silicon oxidation film, forming a spacer insulation film at the lateral side of the exposed region, and defining an activation region, exposing the collector thin film of the activation region using a mask, and forming an auxiliary lateral film for an isolation of the device, forming a selective collector region by ion-implantating a dopant to the activation region which is limited by the auxiliary lateral film, removing the auxiliary lateral film, etching the exposed portion in an anisotropic etching method, and forming a shallow trench for a device isolation, forming a polysilicon lateral film to have a height which is the same as the height of the base electrode polysilicon layer on the shallow trench, and forming a self-aligned base.
摘要翻译：一种用于制造异质结双极晶体管的改进方法，其包括以下步骤：在半导体衬底上形成掩埋集电极，集电极薄膜和集电极沉降片，以形成第一氧化硅膜，基极多晶硅层，氮化物在所得到的基板上暴露第一硅氧化膜的氧化膜，在暴露区域的侧面形成间隔绝缘膜，并限定激活区域，使用掩模曝光激活区域的集电极薄膜，并形成用于隔离器件的辅助横向膜，通过将离子注入到由辅助侧膜限制的活化区域的掺杂剂形成选择性集电极区域，去除辅助横向膜，在各向异性层中蚀刻暴露部分蚀刻方法，以及形成用于器件隔离的浅沟槽，形成多晶硅侧膜以具有s的高度 ame作为浅沟槽上的基极多晶硅层的高度，并形成自对准基底。

2. 发明授权

US5696007A Method for manufacturing a super self-aligned bipolar transistor 失效
标题翻译：用于制造超自对准双极晶体管的方法
公开(公告)号：US5696007A
公开(公告)日：1997-12-09
申请号：US729840
申请日：1996-10-15
申请人： Byung-Ryul Ryum , Tae-Hyeon Han , Deok-Ho Cho , Soo-Min Lee , Kwang-Eui Pyun
发明人： Byung-Ryul Ryum , Tae-Hyeon Han , Deok-Ho Cho , Soo-Min Lee , Kwang-Eui Pyun
IPC分类号： H01L29/73 , H01L21/331 , H01L29/165 , H01L29/70 , H01L29/732 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66242 , H01L29/7378 , Y10S148/072
摘要： The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth and a polycide base electrode without using a trench for isolating between elements, thereby enhancing the performance thereof, which comprises the steps of: forming sequently a first oxidation film, an electrically conducting thin film and a second oxidation film on top of a substrate; patterning the second oxidation film and the conducting thin film to form a preliminary spacer; removing an exposed portion of the first oxidation film, and selectively growing a collector layer; oxidizing the collector layer to form a thermal oxidation film, and removing the preliminary spacer; depositing a polysilicon and forming a silicon oxidation film and a polysilicon spacer on the second oxidation film and the removed portion of the preliminary spacer, respectively; exposing the base thin film, the spacer and the collector layer to form a SiGe/Si layer; forming a base electrode on the SiGe/Si layer; exposing a portion of the first oxidation film and forming a third oxidation film; exposing a surface of the SiGe/Si layer and forming a oxidation spacer on sides of an etched portion, then self-aligning the emitter and the emitter electrode; and performing a metal wiring process.
摘要翻译：本发明涉及一种能够使元件小型化的超自对准异质结双极晶体管的制造方法，通过采用选择性集电体外延生长和多选择性基极电极简化其工艺步骤，而不使用用于隔离元件之间的沟槽，从而提高其性能，其包括以下步骤：在衬底的顶部上顺次形成第一氧化膜，导电薄膜和第二氧化膜; 图案化第二氧化膜和导电薄膜以形成预备间隔物; 去除第一氧化膜的暴露部分，并选择性地生长集电体层; 氧化所述集电体层以形成热氧化膜，并除去所述预备间隔物; 在所述第二氧化膜上分别沉积多晶硅并形成硅氧化膜和多晶硅间隔物和所述预备间隔物的去除部分; 暴露基底薄膜，间隔物和集电极层以形成SiGe / Si层; 在SiGe / Si层上形成基极; 暴露第一氧化膜的一部分并形成第三氧化膜; 暴露SiGe / Si层的表面并在蚀刻部分的侧面上形成氧化间隔物，然后自发对准发射极和发射极; 并执行金属布线处理。

3. 发明授权

US06190984B1 Method for fabricating of super self-aligned bipolar transistor 失效
标题翻译：超自对准双极晶体管的制造方法
公开(公告)号：US06190984B1
公开(公告)日：2001-02-20
申请号：US09229831
申请日：1999-01-13
申请人： Byung-Ryul Ryum , Deok-Ho Cho , Tae-Hyeon Han , Soo-Min Lee , Kwang-Eui Pyun
发明人： Byung-Ryul Ryum , Deok-Ho Cho , Tae-Hyeon Han , Soo-Min Lee , Kwang-Eui Pyun
IPC分类号： H01L218222
CPC分类号： H01L29/66242
摘要： The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.
摘要翻译：本发明涉及一种用于制造能够使元件小型化的超自对准异质结双极晶体管的方法，通过采用选择性集电体外延生长工艺简化其工艺步骤，而不使用用于元件间隔离的沟槽。根据本发明，通过使用限定发射极区域和第二间隔物的掩模来导出元件之间的隔离。基层具有由Si，未掺杂的SiGe，SiGe原位掺杂p型杂质的Si和Si构成的多层结构。此外，不需要基底的选择性外延生长。因此，可能不太容易发生漏电流或发射极 - 基极 - 集电极短路效应。

4. 发明授权

US5668022A Silicon-silicon-germanium heterojunction bipolar transistor fabrication method 失效
标题翻译：硅硅锗异质结双极晶体管制造方法
公开(公告)号：US5668022A
公开(公告)日：1997-09-16
申请号：US700930
申请日：1996-08-23
申请人： Deok-Ho Cho , Soo-Min Lee , Tae-Hyeon Han , Byung-Ryul Ryum , Kwang-Eui Pyun
发明人： Deok-Ho Cho , Soo-Min Lee , Tae-Hyeon Han , Byung-Ryul Ryum , Kwang-Eui Pyun
IPC分类号： H01L29/73 , H01L21/331 , H01L29/165 , H01L29/732 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66242 , H01L29/7378 , Y10S148/072
摘要： A silicon/silicon-germanium bipolar transistor fabrication method employs a metallic silicide film as an extrinsic base electrode to reduce resistance of the extrinsic base electrode, and to increase a maximum oscillation frequency and cut-off frequency due to its self-aligned structure. The fabrication method enables agglomeration to occur on the side wall of the polycrystalline silicon film connected to the metallic silicide film instead of on the interface between the metallic silicide film and the lower silicon/silicon-germanium film, and leads the extrinsic base electrode to be sandwitched by the insulator films, thereby realizing a constant resistance and also resulting in the application of integrated circuits to a mass production mechanism.
摘要翻译：硅/硅 - 锗双极晶体管制造方法使用金属硅化物膜作为外部基极，以降低外部基极的电阻，并且由于其自对准结构而增加最大振荡频率和截止频率。该制造方法可以在连接到金属硅化物膜的多晶硅膜的侧壁上而不是在金属硅化物膜和下硅/硅 - 锗膜之间的界面上发生聚集，并且引导外部基极为由绝缘体膜切割，从而实现恒定的电阻，并且还导致集成电路应用于大规模生产机构。

5. 发明授权

US5962879A Super self-aligned bipolar transistor 失效
标题翻译：超自对准双极晶体管
公开(公告)号：US5962879A
公开(公告)日：1999-10-05
申请号：US854665
申请日：1997-05-12
申请人： Byung-Ryul Ryum , Deok-Ho Cho , Tae-Hyeon Han , Soo-Min Lee , Kwang-Eui Pyun
发明人： Byung-Ryul Ryum , Deok-Ho Cho , Tae-Hyeon Han , Soo-Min Lee , Kwang-Eui Pyun
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/7378
摘要： The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.
摘要翻译：本发明涉及一种用于制造能够使元件小型化的超自对准异质结双极晶体管的方法，通过采用选择性集电体外延生长工艺简化其工艺步骤，而不使用用于元件间隔离的沟槽。根据本发明，通过使用限定发射极区域和第二间隔物的掩模来导出元件之间的隔离。基层具有由Si，未掺杂的SiGe，SiGe原位掺杂p型杂质的Si和Si构成的多层结构。此外，不需要基底的选择性外延生长。因此，可能不太容易发生漏电流或发射极 - 基极 - 集电极短路效应。

6. 发明授权

US06562688B2 Method of manufacturing a bipolar device 失效
标题翻译：制造双极器件的方法
公开(公告)号：US06562688B2
公开(公告)日：2003-05-13
申请号：US09747761
申请日：2000-12-21
申请人： Tae-Hyeon Han , Byung Ryul Ryum , Soo-Min Lee , Deok-Ho Cho
发明人： Tae-Hyeon Han , Byung Ryul Ryum , Soo-Min Lee , Deok-Ho Cho
IPC分类号： H01L21331
CPC分类号： H01L29/66287 , H01L29/66242
摘要： Disclosed are a method for manufacturing a homojunction or heterojunction bipolar device and a structure of the bipolar device manufactured by the method. The method comprises steps of forming a collector on a substrate including a buried collector to be contacted with the buried collector and protruded in the form of an island; depositing a collector dielectric film on the substrate on which the collector is formed; removing a protruded portion of the collector dielectric film covering the substrate; depositing a first semiconductor electrode layer on the substrate including the collector protruded over the collector dielectric film and flatting a surface of the first semiconductor electrode to expose only the collector formed of a semiconductor material and the first semiconductor electrode; and growing a base thin film including one of silicon and silicon-germanium on the substrate on which only the semiconductor material is exposed, thereby preventing the non-uniformity of a thickness of the base thin film, a contain rate of an impurity and a germanium distribution by the loading effect.
摘要翻译：公开了用于制造均质结或异质结双极器件的方法和通过该方法制造的双极器件的结构。该方法包括以下步骤：在包括与埋藏式收集器接触并以岛形式突出的埋地收集器的基板上形成集电器; 在其上形成集电极的基板上沉积集电极电介质膜; 去除覆盖所述基板的所述集电极电介质膜的突出部分; 在包括集电极电介质膜上的集电体的基板上沉积第一半导体电极层，使第一半导体电极的表面平坦化，仅露出由半导体材料形成的集电体和第一半导体电极; 并且在仅在其上仅露出半导体材料的基板上生长包括硅和硅锗之一的基底薄膜，从而防止基底薄膜的厚度不均匀，杂质含量和锗的含量通过负载效应分配。

7. 发明授权

US5874347A Method for fabricating field oxide isolation region for semiconductor devices 失效
标题翻译：半导体器件的场氧化物隔离区域的制造方法
公开(公告)号：US5874347A
公开(公告)日：1999-02-23
申请号：US688283
申请日：1996-07-29
申请人： Byung-Ryul Ryum , Tae-Hyeon Han , Soo-Min Lee , Deok-Ho Cho , Jin-Young Kang
发明人： Byung-Ryul Ryum , Tae-Hyeon Han , Soo-Min Lee , Deok-Ho Cho , Jin-Young Kang
IPC分类号： H01L21/316 , H01L21/32 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/32 , H01L21/76202
摘要： Disclosed is a device isolating method of a semiconductor device, comprising the steps of sequentially forming a pad oxide film, a polysilicon film and an insulating layer, on a silicon substrate, said insulating layer being composed of a first silicon oxide film, a nitride film and a second silicon oxide film formed sequentially on the polysilicon film; defining active and inactive regions by using a patterned photomask; removing the insulating layer only on the inactive region so as to expose a surface of the polysilicon film; forming a side wall at both edges of the insulating layer on the active region, said side wall being composed of a nitride film; depositing a third silicon oxide film on the surface of the polysilicon film; removing the side wall and etching the substrate to a predetermined depth to form a trench; filling an insulating material into the trench and depositing it up to the second silicon oxide so as to form an insulating film for isolating; simultaneously removing the second silicon oxide film and the silicon oxide film and removing the polysilicon film only the inactive region; performing a thermal oxidation to form a field oxide film on the inactive region; and sequentially removing the isolating layer and the polysilicon film formed on the active region. Because the active region is defined using an insulator-filled shallow trench before performing thermal oxidation, no oxygen is penetrated into the active region during the thermal oxidation, whereby a field oxide film can be formed without occurrence of a Bird's beak.
摘要翻译：公开了一种半导体器件的器件隔离方法，包括以下步骤：在硅衬底上顺序形成衬垫氧化膜，多晶硅膜和绝缘层，所述绝缘层由第一氧化硅膜，氮化膜以及顺序地形成在所述多晶硅膜上的第二氧化硅膜; 通过使用图案化的光掩模来定义有源和非活性区域; 仅在非活性区域上去除绝缘层，以暴露多晶硅膜的表面; 在有源区域上的绝缘层的两个边缘处形成侧壁，所述侧壁由氮化物膜构成; 在所述多晶硅膜的表面上沉积第三氧化硅膜; 去除侧壁并将衬底蚀刻到预定深度以形成沟槽; 将绝缘材料填充到沟槽中并将其沉积到第二氧化硅上，以形成用于隔离的绝缘膜; 同时去除第二氧化硅膜和氧化硅膜，并且仅去除多晶硅膜的非活性区域; 进行热氧化以在非活性区域上形成场氧化物膜; 并依次去除形成在有源区上的隔离层和多晶硅膜。由于在进行热氧化之前使用绝缘子填充的浅沟槽限定有源区域，所以在热氧化期间没有氧气渗透到有源区域中，由此可以形成场氧化膜而不发生鸟喙。

8. 发明授权

US5496745A Method for making bipolar transistor having an enhanced trench isolation 失效
标题翻译：制造具有增强的沟槽隔离的双极晶体管的方法
公开(公告)号：US5496745A
公开(公告)日：1996-03-05
申请号：US358825
申请日：1994-12-19
申请人： Byung-Ryul Ryum , Tae-Hyeon Han , Soo-Min Lee , Deok-Ho Cho , Seong-Hearn Lee , Jin-Young Kang
发明人： Byung-Ryul Ryum , Tae-Hyeon Han , Soo-Min Lee , Deok-Ho Cho , Seong-Hearn Lee , Jin-Young Kang
IPC分类号： H01L21/331 , H01L21/762 , H01L21/265
CPC分类号： H01L29/66287 , H01L21/76224 , Y10S148/01 , Y10S148/011 , Y10S148/072
摘要： Disclosed is a fabrication of a bipolar transistor using an enhanced trench isolation so as to improve integration and performance thereof, comprising the steps of sequentially etching back portions corresponding to a trench using a trench forming mask to a predetermined depth of the buried collector to form the trench; filling an isolation insulating layer into the trench; polishing the isolation insulating layer up to a surface of the silicon oxide layer; sequentially forming a second insulating layer on the isolating insulating layer and the silicon oxide layer; removing the first polysilicon layer and the first insulating layer formed on an inactive region other than an active region defined by the trench; thermal-oxidizing the collector layer formed on the inactive region to form a thermal oxide layer; removing the second insulating layer and sequentially forming a third polysilicon, a third insulating layer and a second nitride layer; etching back layers formed on a portion of the first insulating layer to form an opening in the active region; forming a first side wall on both edges of the opening and removing the first insulating layer; forming an intrinsic base at a region where the first insulating layer is removed to electrically connect the intrinsic base with an extrinsic base in self-alignment; forming a second side wall on both sides of the first side wall; and forming an emitter layer on the intrinsic base.
摘要翻译：公开了使用增强的沟槽隔离来改善其集成和性能的双极晶体管的制造，其包括以下步骤：使用沟槽形成掩模将对应于沟槽的部分依次蚀刻到掩埋集电极的预定深度，以形成沟; 将隔离绝缘层填充到沟槽中; 将隔离绝缘层抛光直到氧化硅层的表面; 在隔离绝缘层和氧化硅层上依次形成第二绝缘层; 除去形成在除了由沟槽限定的有源区域之外的非活性区域上的第一多晶硅层和第一绝缘层; 对形成在非活性区域上的集电体层进行热氧化以形成热氧化物层; 去除所述第二绝缘层并顺序地形成第三多晶硅，第三绝缘层和第二氮化物层; 蚀刻形成在所述第一绝缘层的一部分上的层以在所述有源区中形成开口; 在所述开口的两个边缘上形成第一侧壁并移除所述第一绝缘层; 在去除所述第一绝缘层的区域上形成本征基极以使所述本征基极与自对准的外部基极电连接; 在所述第一侧壁的两侧上形成第二侧壁; 并在本征基底上形成发射极层。

9. 发明授权

US06552374B2 Method of manufacturing bipolar device and structure thereof 失效
公开(公告)号：US06552374B2
公开(公告)日：2003-04-22
申请号：US09765499
申请日：2001-01-17
申请人： Tae-Hyeon Han , Byung Ryul Ryum , Soo-Min Lee , Deok-Ho Cho
发明人： Tae-Hyeon Han , Byung Ryul Ryum , Soo-Min Lee , Deok-Ho Cho
IPC分类号： H01L31072
CPC分类号： H01L29/66287 , H01L29/7322
摘要： Disclosed are a method for forming a base layer by epitaxial growth technology of a heterojunction bipolar device and a structure of the bipolar device manufactured by the method. The method comprises steps of depositing an insulation film containing silicon nitride on a substrate and removing a part of the insulation film to define a collector area; growing a first semiconductor in the collector area by selective epitaxial growth method to form the collector protruded over the insulation film in the form of a mushroom; forming an oxide film containing silicon dioxide on a surface of the collector protruded over the silicon nitride; selectively growing a second polycrystalline semiconductor material on only the nitride insulation film at the same height as the protruded portion of the collector to form a first base semiconductor electrode; removing an upper surface of the oxide film to expose the collector; and growing a second semiconductor containing silicon-germanium on the second polycrystalline semiconductor and the collector of the first semiconductor to form a second base semiconductor electrode on the first base semiconductor electrode and the base on the collector, thereby preventing a current leakage and a loading effect.

10. 发明授权

US5696020A Method for fabricating semiconductor device isolation region using a trench mask 失效
标题翻译：使用沟槽掩模制造半导体器件隔离区域的方法
公开(公告)号：US5696020A
公开(公告)日：1997-12-09
申请号：US470479
申请日：1995-06-05
申请人： Byung-Ryul Ryum , Tae-Hyeon Han , Soo-Min Lee , Deok-Ho Cho , Jin-Young Kang
发明人： Byung-Ryul Ryum , Tae-Hyeon Han , Soo-Min Lee , Deok-Ho Cho , Jin-Young Kang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/76202
摘要： Disclosed is a device isolating method of a semiconductor device, comprising the steps of sequentially forming a pad oxide film, a polysilicon film and an insulating layer, on a silicon substrate, said insulating layer being composed of a first silicon oxide film, a nitride film and a second silicon oxide film formed sequentially on the polysilicon film; defining active and inactive regions by using a patterned photomask; removing the insulating layer only on the inactive region so as to expose a surface of the polysilicon film; forming a side wall at both edges of the insulating layer on the active region, said side wall being composed of a nitride film; depositing a third silicon oxide film on the surface of the polysilicon film; removing the side wall and etching the substrate to a predetermined depth to form a trench; filling an insulating material into the trench and depositing it up to the second silicon oxide so as to form an insulating film for isolating; simultaneously removing the second silicon oxide film and the silicon oxide film and removing the polysilicon film only the inactive region; performing a thermal oxidation to form a field oxide film on the inactive region; and sequentially removing the isolating layer and the polysilicon film formed on the active region. Because the active region is defined using an insulator-filled shallow trench before performing thermal oxidation, no oxygen is penetrated into the active region during the thermal oxidation, whereby a field oxide film can be formed without occurrence of a Bird's beak.
摘要翻译：公开了一种半导体器件的器件隔离方法，包括以下步骤：在硅衬底上顺序形成衬垫氧化膜，多晶硅膜和绝缘层，所述绝缘层由第一氧化硅膜，氮化膜以及顺序地形成在所述多晶硅膜上的第二氧化硅膜; 通过使用图案化的光掩模来定义有源和非活性区域; 仅在非活性区域上去除绝缘层，以暴露多晶硅膜的表面; 在有源区域上的绝缘层的两个边缘处形成侧壁，所述侧壁由氮化物膜构成; 在所述多晶硅膜的表面上沉积第三氧化硅膜; 去除侧壁并将衬底蚀刻到预定深度以形成沟槽; 将绝缘材料填充到沟槽中并将其沉积到第二氧化硅上，以形成用于隔离的绝缘膜; 同时去除第二氧化硅膜和氧化硅膜，并且仅去除多晶硅膜的非活性区域; 进行热氧化以在非活性区域上形成场氧化物膜; 并依次去除形成在有源区上的隔离层和多晶硅膜。由于在进行热氧化之前使用绝缘子填充的浅沟槽限定有源区域，所以在热氧化期间没有氧气渗透到有源区域中，由此可以形成场氧化膜而不发生鸟喙。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式