专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09727521B2 Efficient CPU mailbox read access to GPU memory 有权
公开(公告)号：US09727521B2
公开(公告)日：2017-08-08
申请号：US13620232
申请日：2012-09-14
申请人： Dennis K. Ma , Karan Gupta , Lei Tian , Franck R. Diard , Praveen Jain , Wei-Je Huang , Atul Kalambur
发明人： Dennis K. Ma , Karan Gupta , Lei Tian , Franck R. Diard , Praveen Jain , Wei-Je Huang , Atul Kalambur
IPC分类号： G06F15/167 , G06F15/16 , G06F15/163 , G06F15/173 , G06F15/17
CPC分类号： G06F15/167 , G06F15/16 , G06F15/163 , G06F15/17 , G06F15/173
摘要： Techniques are disclosed for peer-to-peer data transfers where a source device receives a request to read data words from a target device. The source device creates a first and second read command for reading a first portion and a second portion of a plurality of data words from the target device, respectively. The source device transmits the first read command to the target device, and, before a first read operation associated with the first read command is complete, transmits the second read command to the target device. The first and second portions of the plurality of data words are stored in a first and second portion a buffer memory, respectively. Advantageously, an arbitrary number of multiple read operations may be in progress at a given time without using multiple peer-to-peer memory buffers. Performance for large data block transfers is improved without consuming peer-to-peer memory buffers needed by other peer GPUs.

2. 发明申请

US20100153658A1 Deadlock Avoidance By Marking CPU Traffic As Special 有权
标题翻译：通过将CPU流量标记为特殊来防止死锁
公开(公告)号：US20100153658A1
公开(公告)日：2010-06-17
申请号：US12334394
申请日：2008-12-12
申请人： Samuel H. Duncan , David B. Glasco , Wei-je Huang , Atul Kalambur , Patrick R. Marchand , Dennis K. Ma
发明人： Samuel H. Duncan , David B. Glasco , Wei-je Huang , Atul Kalambur , Patrick R. Marchand , Dennis K. Ma
IPC分类号： G06F12/08
CPC分类号： G06F13/4221 , G06F9/3877 , G06F13/1663
摘要： Deadlocks are avoided by marking read requests issued by a parallel processor to system memory as “special.” Read completions associated with read requests marked as special are routed on virtual channel 1 of the PCIe bus. Data returning on virtual channel 1 cannot become stalled by write requests in virtual channel 0, thus avoiding a potential deadlock.
摘要翻译：通过将由并行处理器发出的读取请求标记为系统内存作为“特殊”来避免死锁。读取完成与读取请求相关联，标记为特殊的请求在PCIe总线的虚拟通道1上路由。虚拟通道1上返回的数据不能因虚拟通道0中的写入请求而停止，从而避免潜在的死锁。

3. 发明授权

US08392667B2 Deadlock avoidance by marking CPU traffic as special 有权
标题翻译：通过将CPU流量标记为特殊来防止死锁
公开(公告)号：US08392667B2
公开(公告)日：2013-03-05
申请号：US12334394
申请日：2008-12-12
申请人： Samuel H. Duncan , David B. Glasco , Wei-Je Huang , Atul Kalambur , Patrick R. Marchand , Dennis K. Ma
发明人： Samuel H. Duncan , David B. Glasco , Wei-Je Huang , Atul Kalambur , Patrick R. Marchand , Dennis K. Ma
IPC分类号： G06F12/00
CPC分类号： G06F13/4221 , G06F9/3877 , G06F13/1663
摘要： Deadlocks are avoided by marking read requests issued by a parallel processor to system memory as “special.” Read completions associated with read requests marked as special are routed on virtual channel 1 of the PCIe bus. Data returning on virtual channel 1 cannot become stalled by write requests in virtual channel 0, thus avoiding a potential deadlock.
摘要翻译：通过将并行处理器向系统内存发出的读取请求作为特殊标记来避免死锁。与PCIe总线的虚拟通道1相连的读取完成与标记为特殊的读请求相关联。虚拟通道1上返回的数据不能因虚拟通道0中的写入请求而停止，从而避免潜在的死锁。

4. 发明授权

US09424227B2 Providing byte enables for peer-to-peer data transfer within a computing environment 有权
标题翻译：提供字节可以在计算环境中进行对等数据传输
公开(公告)号：US09424227B2
公开(公告)日：2016-08-23
申请号：US13541633
申请日：2012-07-03
申请人： Samuel H. Duncan , Dennis K. Ma , Wei-Je Huang , Gary Ward
发明人： Samuel H. Duncan , Dennis K. Ma , Wei-Je Huang , Gary Ward
IPC分类号： G06F15/173 , G06F15/167 , G06F15/16 , G06F15/163 , G06F15/17
CPC分类号： G06F15/167 , G06F15/16 , G06F15/163 , G06F15/17 , G06F15/173
摘要： Non-contiguous or tiled payload data are efficiently transferred between peers over a fabric. Specifically, a client transfers a byte enable message to a peer device via a mailbox mechanism, where the byte enable message specifies which bytes of the payload data being transferred via the data packet are to be written to the frame buffer on the peer device and which bytes are not to be written. The client transfers the non-contiguous or tiled payload payload data to the peer device. Upon receiving the payload data, the peer device writes bytes from the payload data into the target frame buffer for only those bytes enabled via the byte enable message. One advantage of the present invention is that non-contiguous or tiled data are transferred over a fabric with improved efficiency.
摘要翻译：非连续或平铺的有效载荷数据可以通过一个结构在对等体之间有效传输。具体来说，客户端通过邮箱机制向对等设备传送字节使能消息，其中字节使能消息指定要经由数据包传送的有效载荷数据的哪些字节将被写入对等设备上的帧缓冲器，以及哪个字节不被写入。客户端将非连续或平铺的有效载荷有效载荷数据传输到对等设备。在接收到有效载荷数据时，对等设备将字节从有效载荷数据写入目标帧缓冲器，以便仅通过字节使能消息使能的字节。本发明的一个优点在于，不连续的或平铺的数据以提高的效率在织物上传送。

5. 发明授权

US07467289B1 Indicating acknowledge of stable state of pipeline resource when freeze bit set and context switch inhibited 有权
标题翻译：指示当冻结位设置和上下文切换禁止时管道资源稳定状态的确认
公开(公告)号：US07467289B1
公开(公告)日：2008-12-16
申请号：US11553913
申请日：2006-10-27
申请人： Lincoln G. Garlick , Vikramjeet Singh , David W. Nuechterlein , Shail Dave , Jeffrey M. Smith , Paolo E. Sabella , Dennis K. Ma
发明人： Lincoln G. Garlick , Vikramjeet Singh , David W. Nuechterlein , Shail Dave , Jeffrey M. Smith , Paolo E. Sabella , Dennis K. Ma
IPC分类号： G06F11/30
CPC分类号： G06F9/485
摘要： Software can freeze portions of a pipeline operation in a processor by asserting a predetermined freeze register in the processor. The processor halts operations relating to portions of a common pipeline processing in response to an asserted freeze register. Processor resources that operate downstream from the common pipeline continue to process any scheduled instructions. The processor is prevented from initiating any context switching in which a processor resource is allocated to a different channel. The processor stops supplying any additional data to downstream resources and ensures that the interface to downstream resources is clear of previously sent data. The processor prevents state machines from making additional requests. The processor asserts an acknowledgement indication in response to the freeze assertion when the processing has reached a stable state. Software is allowed to manipulate states and registers within the processor. Clearing the freeze register allows processing to resume.
摘要翻译：软件可以通过在处理器中断言预定的冻结寄存器来冻结处理器中流水线操作的部分。响应于断言的冻结寄存器，处理器停止与公共流水线处理的部分有关的操作。在公共管道下游运行的处理器资源继续处理任何计划的指令。防止处理器发起其中将处理器资源分配给不同信道的任何上下文切换。处理器停止向下游资源提供任何附加数据，并确保与下游资源的接口清除以前发送的数据。处理器可防止状态机发出其他请求。当处理已经达到稳定状态时，处理器响应于冻结断言声明确认指示。允许软件在处理器内操纵状态和寄存器。清除冻结寄存器允许处理恢复。

6. 发明授权

US09164766B1 System and method for hardware assisted stack 有权
标题翻译：硬件辅助堆栈的系统和方法
公开(公告)号：US09164766B1
公开(公告)日：2015-10-20
申请号：US11102189
申请日：2005-04-08
申请人： Aron L. Wong , Dennis K. Ma , Jonah M. Alben , Mark S. Krueger , Jeffrey J. Irwin
发明人： Aron L. Wong , Dennis K. Ma , Jonah M. Alben , Mark S. Krueger , Jeffrey J. Irwin
IPC分类号： G06F9/30
CPC分类号： G06F9/30134 , G06F9/4401 , G06F9/5016 , G06F2209/509
摘要： Methods and apparatus for providing additional storage, in the form of a hardware assisted stack, usable by software running an environment with limited resources. As an example, the hardware assisted stack may provide additional stack space to VBIOS code that is accessible within its limited allocated address space.
摘要翻译：用于以硬件辅助堆栈的形式提供附加存储的方法和装置，其可由运行有限资源的环境的软件使用。作为示例，硬件辅助堆栈可以向在其有限的分配的地址空间内可访问的VBIOS代码提供额外的堆栈空间。

7. 发明授权

US08547993B1 Asynchronous interface for communicating between clock domains 有权
标题翻译：用于在时钟域之间通信的异步接口
公开(公告)号：US08547993B1
公开(公告)日：2013-10-01
申请号：US11463682
申请日：2006-08-10
申请人： Lincoln G. Garlick , Richard A. Silkebakken , Prakash G. Apte , Paolo E. Sabella , Samuel H. Duncan , Dennis K. Ma , Sean J. Treichler
发明人： Lincoln G. Garlick , Richard A. Silkebakken , Prakash G. Apte , Paolo E. Sabella , Samuel H. Duncan , Dennis K. Ma , Sean J. Treichler
IPC分类号： H04L12/66 , H04L29/06
CPC分类号： H04L29/06 , G06F13/4226
摘要： Methods, apparatuses, and systems are presented for performing asynchronous communications involving using an asynchronous interface to send signals between a source device and a plurality of client devices, the source device and the plurality of client devices being part of a processing unit capable of performing graphics operations, the source device being coupled to the plurality of client devices using the asynchronous interface, wherein the asynchronous interface includes at least one request signal, at least one address signal, at least one acknowledge signal, and at least one data signal, and wherein the asynchronous interface operates in accordance with at least one programmable timing characteristic associated with the source device.
摘要翻译：呈现用于执行涉及使用异步接口在源设备和多个客户端设备之间发送信号的异步通信的方法，设备和系统，源设备和多个客户端设备是能够执行图形的处理单元的一部分所述源设备使用所述异步接口耦合到所述多个客户端设备，其中所述异步接口包括至少一个请求信号，至少一个地址信号，至少一个确认信号和至少一个数据信号，并且其中异步接口根据与源设备相关联的至少一个可编程定时特性进行操作。

8. 发明授权

US08108879B1 Method and apparatus for context switching of multiple engines 有权
标题翻译：多台发动机上下文切换的方法和装置
公开(公告)号：US08108879B1
公开(公告)日：2012-01-31
申请号：US11553901
申请日：2006-10-27
申请人： Lincoln G. Garlick , Dennis K. Ma , Paolo E. Sabella , David W. Nuechterlein
发明人： Lincoln G. Garlick , Dennis K. Ma , Paolo E. Sabella , David W. Nuechterlein
IPC分类号： G06F9/46
CPC分类号： G06F9/52
摘要： A processor having multiple independent engines can concurrently support a number of independent processes or operation contexts. The processor can independently schedule instructions for execution by the engines. The processor can independently switch the operation context that an engine supports. The processor can maintain the integrity of the operations performed and data processed by each engine during a context switch by controlling the manner in which the engine transitions from one operation context to the next. The processor can wait for the engine to complete processing of pipelined instructions of a first context before switching to another context, or the processor can halt the operation of the engine in the midst of one or more instructions to allow the engine to execute instructions corresponding to another context. The processor can affirmatively verify completion of tasks for a specific operation context.
摘要翻译：具有多个独立引擎的处理器可以同时支持多个独立的进程或操作上下文。处理器可以独立地调度指令以供引擎执行。处理器可以独立地切换引擎支持的操作上下文。处理器可以通过控制引擎从一个操作上下文转换到下一个操作上下文的方式来保持在上下文切换期间由每个引擎执行的操作和数据处理的完整性。处理器可以等待引擎在切换到另一个上下文之前完成对第一上下文的流水线指令的处理，或者处理器可以在一个或多个指令中停止发动机的操作，以允许引擎执行对应于另一个上下文。处理器可以肯定地验证特定操作上下文的任务完成。

9. 发明授权

US07483032B1 Zero frame buffer 有权
标题翻译：零帧缓冲区
公开(公告)号：US07483032B1
公开(公告)日：2009-01-27
申请号：US11253438
申请日：2005-10-18
申请人： Sonny S. Yeoh , Shane J. Keil , Dennis K. Ma , Peter C. Tong
发明人： Sonny S. Yeoh , Shane J. Keil , Dennis K. Ma , Peter C. Tong
IPC分类号： G06F12/00 , G06F15/16 , G06F12/08
CPC分类号： G09G5/363
摘要： Circuits, methods, and apparatus that allow the elimination of a frame buffer connected directly to a graphics processing unit. The graphics processing unit includes an on-chip memory. Following system power-up or reset, the GPU initially renders comparatively low-resolution images to the on-chip memory for display. Afterward, the GPU renders images, which are typically higher resolution, and stores them in a system memory, apart from the graphics processing unit. The on-chip memory, which is no longer needed for image storage, instead stores address information, referred to as page tables, identifying the location of data stored by the GPU in the separate system memory.
摘要翻译：允许消除直接连接到图形处理单元的帧缓冲器的电路，方法和装置。图形处理单元包括片上存储器。在系统上电或复位后，GPU最初将相对较低分辨率的图像呈现给片上存储器进行显示。之后，GPU将呈现通常较高分辨率的图像，并将它们存储在除了图形处理单元之外的系统存储器中。不再需要用于图像存储的片上存储器，而是存储称为页表的地址信息，其将GPU存储的数据的位置识别在单独的系统存储器中。

10. 发明申请

US20080028181A1 DEDICATED MECHANISM FOR PAGE MAPPING IN A GPU 审中-公开
标题翻译：用于在GPU中进行页面映射的专用机制
公开(公告)号：US20080028181A1
公开(公告)日：2008-01-31
申请号：US11689485
申请日：2007-03-21
申请人： Peter C. Tong , Sonny S. Yeoh , Kevin J. Kranzusch , Gary D. Lorensen , Kaymann L. Woo , Ashish Kishen Kaul , Colyn S. Case , Stefan A. Gottschalk , Dennis K. Ma
发明人： Peter C. Tong , Sonny S. Yeoh , Kevin J. Kranzusch , Gary D. Lorensen , Kaymann L. Woo , Ashish Kishen Kaul , Colyn S. Case , Stefan A. Gottschalk , Dennis K. Ma
IPC分类号： G06F12/00
CPC分类号： G06F3/14 , G06F12/1027 , G06F2212/654 , G06T1/60 , G09G5/36 , G09G5/363 , G09G2330/026 , G09G2360/121 , G09G2360/125
摘要： Circuits, methods, and apparatus that reduce or eliminate system memory accesses to retrieve address translation information. In one example, these accesses are reduced or eliminated by pre-populating a graphics TLB with entries that are used to translate virtual addresses used by a GPU to physical addresses used by a system memory. Translation information is maintained by locking or restricting entries in the graphics TLB that are needed for display access. This may be done by limiting access to certain locations in the graphics TLB, by storing flags or other identifying information in the graphics TLB, or by other appropriate methods. In another example, memory space is allocated by a system BIOS for a GPU, which stores a base address and address range. Virtual addresses in the address range are translated by adding them to the base address.
摘要翻译：减少或消除系统存储器访问以检索地址转换信息的电路，方法和装置。在一个示例中，通过用用于将GPU使用的虚拟地址转换为系统存储器使用的物理地址的条目预先填充图形TLB来减少或消除这些访问。通过锁定或限制显示访问所需的图形TLB中的条目来维护翻译信息。这可以通过在图形TLB中限制对图形TLB中的某些位置的访问，通过在图形TLB中存储标志或其他识别信息，或通过其他适当的方法来实现。在另一示例中，内存空间由用于存储基地址和地址范围的GPU的系统BIOS分配。将地址范围中的虚拟地址添加到基地址中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式