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1. 发明授权

US09727521B2 Efficient CPU mailbox read access to GPU memory 有权
公开(公告)号：US09727521B2
公开(公告)日：2017-08-08
申请号：US13620232
申请日：2012-09-14
申请人： Dennis K. Ma , Karan Gupta , Lei Tian , Franck R. Diard , Praveen Jain , Wei-Je Huang , Atul Kalambur
发明人： Dennis K. Ma , Karan Gupta , Lei Tian , Franck R. Diard , Praveen Jain , Wei-Je Huang , Atul Kalambur
IPC分类号： G06F15/167 , G06F15/16 , G06F15/163 , G06F15/173 , G06F15/17
CPC分类号： G06F15/167 , G06F15/16 , G06F15/163 , G06F15/17 , G06F15/173
摘要： Techniques are disclosed for peer-to-peer data transfers where a source device receives a request to read data words from a target device. The source device creates a first and second read command for reading a first portion and a second portion of a plurality of data words from the target device, respectively. The source device transmits the first read command to the target device, and, before a first read operation associated with the first read command is complete, transmits the second read command to the target device. The first and second portions of the plurality of data words are stored in a first and second portion a buffer memory, respectively. Advantageously, an arbitrary number of multiple read operations may be in progress at a given time without using multiple peer-to-peer memory buffers. Performance for large data block transfers is improved without consuming peer-to-peer memory buffers needed by other peer GPUs.

2. 发明申请

US20140082120A1 EFFICIENT CPU MAILBOX READ ACCESS TO GPU MEMORY 有权
标题翻译：高效的CPU邮箱读取访问GPU内存
公开(公告)号：US20140082120A1
公开(公告)日：2014-03-20
申请号：US13620232
申请日：2012-09-14
申请人： Dennis K. MA , Karan Gupta , Lei Tian , Franck R. Diard , Praveen Jain , Wei-Je Huang , Atul Kalambur
发明人： Dennis K. MA , Karan Gupta , Lei Tian , Franck R. Diard , Praveen Jain , Wei-Je Huang , Atul Kalambur
IPC分类号： G06F15/167
CPC分类号： G06F15/167 , G06F15/16 , G06F15/163 , G06F15/17 , G06F15/173
摘要： Techniques are disclosed for peer-to-peer data transfers where a source device receives a request to read data words from a target device. The source device creates a first and second read command for reading a first portion and a second portion of a plurality of data words from the target device, respectively. The source device transmits the first read command to the target device, and, before a first read operation associated with the first read command is complete, transmits the second read command to the target device. The first and second portions of the plurality of data words are stored in a first and second portion a buffer memory, respectively. Advantageously, an arbitrary number of multiple read operations may be in progress at a given time without using multiple peer-to-peer memory buffers. Performance for large data block transfers is improved without consuming peer-to-peer memory buffers needed by other peer GPUs.
摘要翻译：公开了用于对等数据传输的技术，其中源设备从目标设备接收到读取数据字的请求。源设备分别创建用于从目标设备读取多个数据字的第一部分和第二部分的第一和第二读取命令。源设备向目标设备发送第一读取命令，并且在与第一读取命令相关联的第一读取操作完成之前，将第二读取命令发送到目标设备。多个数据字的第一和第二部分分别存储在缓冲存储器的第一和第二部分中。有利地，任意数量的多个读取操作可以在给定时间进行，而不使用多个对等存储器缓冲器。改进了大数据块传输的性能，而不消耗其他对等GPU所需的对等内存缓冲区。

3. 发明授权

US10386396B2 Hybrid PLL for grid synchronization in distributed generation 有权
公开(公告)号：US10386396B2
公开(公告)日：2019-08-20
申请号：US14875993
申请日：2015-10-06
申请人： Suzan Eren , Majid Pahlevaninezhad , Shangzhi Pan , Praveen Jain
发明人： Suzan Eren , Majid Pahlevaninezhad , Shangzhi Pan , Praveen Jain
IPC分类号： G01R23/02 , H03L7/08 , H02J3/38 , G01R25/00 , G01R23/20 , H03L5/00
摘要： Systems, methods, and devices relating to the extraction of parameters for a grid voltage. A multi-block hybrid PLL or hybrid observer receives grid voltage. The grid voltage is received by a harmonic/noise decomposer block which separates the harmonic/noise component of the incoming voltage from the clean voltage signal. The clean voltage signal is then output from the PLL/observer. The clean voltage signal is also sent to an amplitude estimator block which estimates the amplitude of the clean voltage signal. The harmonic/noise component of the input voltage signal is sent, along with the clean voltage signal, to a frequency estimator block. The frequency estimator block then determines the phase angle of the incoming signal as well as the frequency of the incoming voltage signal.

4. 发明授权

US09887640B2 DC-eliminating current controller for grid-connected DC/AC converters 有权
公开(公告)号：US09887640B2
公开(公告)日：2018-02-06
申请号：US14699398
申请日：2015-04-29
申请人： Suzan Eren , Majid Pahlevaninezhad , Shangzhi Pan , Praveen Jain
发明人： Suzan Eren , Majid Pahlevaninezhad , Shangzhi Pan , Praveen Jain
IPC分类号： H02M7/5387 , H02M7/537 , H02M1/12 , H02M7/48
CPC分类号： H02M7/5387 , H02M1/12 , H02M1/126 , H02M7/537 , H02M2007/4803 , Y02B70/1441
摘要： Systems, methods, and devices which eliminate the DC current from the output of grid-connected inverters. A current controller is provided which interfaces with a grid-connected DC/AC inverter. The current controller uses a nonlinear adaptive filter which receives, as input, the output current of the inverter along with grid current frequency. The nonlinear adaptive filter estimates the DC value of the grid current and, in conjunction with an integrator, removes this DC current component. This is done by adjusting the duty cycle of the grid-connected inverter.

5. 发明授权

US09804627B2 Multi-input PV inverter with independent MPPT and minimum energy storage 有权
公开(公告)号：US09804627B2
公开(公告)日：2017-10-31
申请号：US14562429
申请日：2014-12-05
申请人： Shangzhi Pan , Majid Pahlevaninezhad , Praveen Jain
发明人： Shangzhi Pan , Majid Pahlevaninezhad , Praveen Jain
IPC分类号： H02J1/00 , H02J3/00 , G05F1/67 , H02M3/337 , H02J3/38
CPC分类号： G05F1/67 , H02J3/385 , H02M3/3376 , Y02E10/58 , Y10T307/707
摘要： Systems, methods, and devices relating to the use of multiple DC power generation sources with DC/DC converters to thereby provide AC power suitable for provision to a power grid. Multiple DC power generation sources are each coupled to an input stage with a DC/DC converter. All the DC/DC converters in the multiple input stages are controlled by a single digital controller. Within the single digital controller are controller sub-blocks, each of which generates control signals for a specific DC/DC converter. Each controller sub-block provides multiple functions for improving the performance of the system as a whole.

6. 发明授权

US09590531B2 ZVS voltage source inverter with reduced output current ripple 有权
标题翻译： ZVS电压源逆变器具有降低的输出电流纹波
公开(公告)号：US09590531B2
公开(公告)日：2017-03-07
申请号：US14621736
申请日：2015-02-13
申请人： Majid Pahlevaninezhad , Shangzhi Pan , Praveen Jain
发明人： Majid Pahlevaninezhad , Shangzhi Pan , Praveen Jain
IPC分类号： H02M7/5387 , H02M1/14 , H02M1/00
CPC分类号： H02M7/5387 , H02M1/14 , H02M7/53871 , H02M2001/0054 , H02M2001/0058 , Y02B70/1491
摘要： Systems, methods, and devices relating to DC/AC converters. A circuit including a full bridge inverter is provided. One leg of power semiconductor subcircuits of the inverter is switched at line frequency while the other leg is soft switched at a higher frequency using an auxiliary circuit. A control system is used to calculate this higher optimal frequency. To minimize the output current ripple in the output filter, the output inductor is coupled to the auxiliary inductor in the auxiliary circuit.
摘要翻译：与DC / AC转换器相关的系统，方法和设备。提供了包括全桥逆变器的电路。逆变器的一条支路的功率半导体子电路以线路频率切换，而另一条支路使用辅助电路以更高的频率软切换。控制系统用于计算更高的最佳频率。为了最小化输出滤波器中的输出电流纹波，输出电感耦合到辅助电路中的辅助电感器。

7. 发明授权

US09543859B2 System and method for active/reactive power compensation 有权
标题翻译：有功/无功补偿的系统和方法
公开(公告)号：US09543859B2
公开(公告)日：2017-01-10
申请号：US14604412
申请日：2015-01-23
申请人： Suzan Eren , Majid Pahlevaninezhad , Praveen Jain , Alireza Bakhshai
发明人： Suzan Eren , Majid Pahlevaninezhad , Praveen Jain , Alireza Bakhshai
IPC分类号： H02M7/797 , H02M7/5387
CPC分类号： H02M7/797 , H02J3/18 , H02M7/53871 , H02M2007/53876 , Y02E40/30
摘要： Systems, methods, and devices for use with active/reactive power control in power conditioning systems. To provide quick active/reactive power control by way of a grid-connected inverter, an estimator estimates the P and Q coefficients based on an instantaneous power from the grid-connected inverter. The estimator receives grid current and voltage and estimates of the P and Q coefficients are used with reference P and Q values to determine whether active or reactive power needs to be injected to the grid. The P coefficient is a DC offset of the instantaneous power of the grid and the Q coefficient is the coefficient of a sine component of the instantaneous power.
摘要翻译：用于功率调节系统中的有功/无功功率控制的系统，方法和装置。为了通过并网逆变器提供快速有功/无功功率控制，估计器基于并网逆变器的瞬时功率来估计P和Q系数。估计器接收电网电流和电压，并使用P和Q系数的估计与参考P和Q值来确定有功或无功功率是否需要注入电网。 P系数是电网的瞬时功率的直流偏移，Q系数是瞬时功率的正弦分量的系数。

8. 发明授权

US09343600B2 Integrated microinverter housing for a PV AC module 有权
标题翻译：用于PV交流电模块的集成微逆变器外壳
公开(公告)号：US09343600B2
公开(公告)日：2016-05-17
申请号：US14562128
申请日：2014-12-05
申请人： Haibo Zhang , Jan Dressel , Praveen Jain , Majid Pahlevaninezhad , Shangzhi Pan
发明人： Haibo Zhang , Jan Dressel , Praveen Jain , Majid Pahlevaninezhad , Shangzhi Pan
IPC分类号： H05K7/20 , H01L31/024 , H02J3/38 , H02S40/34 , H02S40/32 , H02S40/42
CPC分类号： H01L31/024 , H02J3/383 , H02S40/32 , H02S40/34 , H02S40/425 , Y02E10/50 , Y02E10/563
摘要： Systems and devices relating to an integrated housing for microinverters. The housing has a cavity for housing the circuitry of the microinverter. The housing is mountable on a back sheet of a PV module by way of the housing's top cover. An opening at the back of the housing accommodates DC contacts coming from the PV module while a void configured for an output port is also present in the housing. When mounted on the PV module, the housing is spaced apart from the module.
摘要翻译：与微型转换器集成住房相关的系统和设备。壳体具有用于容纳微逆变器的电路的空腔。外壳可通过外壳的顶盖安装在光伏组件的背板上。壳体后部的开口容纳来自PV模块的DC触点，而在外壳中也存在配置为输出端口的空隙。当安装在PV模块上时，壳体与模块间隔开。

9. 发明授权

US08644035B2 Load adaptive variable frequency phase-shift full-bridge DC/DC converter 有权
标题翻译：负载自适应可变频移相全桥DC / DC转换器
公开(公告)号：US08644035B2
公开(公告)日：2014-02-04
申请号：US13404167
申请日：2012-02-24
申请人： Majid Pahlevaninezhad , Praveen Jain
发明人： Majid Pahlevaninezhad , Praveen Jain
IPC分类号： H02M3/335
CPC分类号： H02M3/337
摘要： Systems, methods, and circuits for providing zero voltage switching conditions across all load conditions in a full-bridge DC/DC converter. An asymmetric auxiliary circuit is provided and the reactive current due to the auxiliary circuit is controlled across various load conditions. This is done by adaptively adjusting the switching frequency of the converter as well as the phase shift of the rising edges of the waveforms for activating the gates in the leading and lagging legs of the full bridge converter.
摘要翻译：用于在全桥DC / DC转换器中的所有负载条件下提供零电压开关条件的系统，方法和电路。提供了非对称辅助电路，并且在各种负载条件下控制由辅助电路引起的无功电流。这通过自适应地调整转换器的开关频率以及用于激活全桥转换器的前导和滞后支路中的门的波形的上升沿的相移来完成。

10. 发明申请

US20130235631A1 ZERO VOLTAGE SWITCHING INTERLEAVED BOOST AC/DC CONVERTER 有权
标题翻译：零电压开关交流升压AC / DC转换器
公开(公告)号：US20130235631A1
公开(公告)日：2013-09-12
申请号：US13415931
申请日：2012-03-09
申请人： Majid Pahlevaninezhad , Praveen Jain
发明人： Majid Pahlevaninezhad , Praveen Jain
IPC分类号： H02M1/42
CPC分类号： H02M1/42 , H02M1/4225 , H02M3/1584 , Y02B70/12 , Y02B70/126
摘要： Circuits and methods relating to the provision of a reactive current to ensure zero voltage switching in a boost power factor correction converter. A simple passive circuit using a series connected inductor and capacitor are coupled between two phases of an interleaved boost PFC converter. The passive circuit takes advantage of the 180° phase-shift between the two phases to provide reactive current for zero voltage switching. A control system for adjusting and controlling the reactive current to ensure ZVS for different loads and line voltages is also provided.
摘要翻译：与提供无功电流相关的电路和方法，以确保升压功率因数校正转换器中的零电压开关。使用串联连接的电感器和电容器的简单无源电路耦合在交错升压PFC转换器的两相之间。无源电路利用两相之间的180°相移来为零电压开关提供无功电流。还提供了一种用于调节和控制无功电流以确保不同负载和线路电压的ZVS的控制系统。

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