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1. 发明授权

US07620126B2 Method and apparatus for detecting frequency lock in a system including a frequency synthesizer 失效
标题翻译：用于检测包括频率合成器的系统中的频率锁定的方法和装置
公开(公告)号：US07620126B2
公开(公告)日：2009-11-17
申请号：US11236658
申请日：2005-09-27
申请人： David William Boerstler , Matthew E. Fernsler , Eskinder Hailu , Jieming Qi , Mack Wayne Riley
发明人： David William Boerstler , Matthew E. Fernsler , Eskinder Hailu , Jieming Qi , Mack Wayne Riley
IPC分类号： H03D3/18
CPC分类号： H03L7/093 , H03L7/095
摘要： A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.
摘要翻译：公开了一种频率合成器锁定检测系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。

2. 发明授权

US07590194B2 Information handling system capable of detecting frequency lock of signals downstream from a signal synthesized by frequency synthesizer 失效
标题翻译：信号处理系统能够检测由频率合成器合成的信号下行信号的频率锁定
公开(公告)号：US07590194B2
公开(公告)日：2009-09-15
申请号：US11236834
申请日：2005-09-27
申请人： David William Boerstler , Matthew E. Fernsler , Eskinder Hailu , Jieming Qi , Mack Wayne Riley
发明人： David William Boerstler , Matthew E. Fernsler , Eskinder Hailu , Jieming Qi , Mack Wayne Riley
IPC分类号： H03D3/18
CPC分类号： G06F1/10 , H03L7/095
摘要： An information handling system including a frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.
摘要翻译：公开了一种包括频率合成器锁定检测系统的信息处理系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。

3. 发明申请

US20080272820A1 Circuit to Reduce Transient Current Swings During Mode Transitions of High Frequency/High Power Chips 有权
标题翻译：在高频/高功率芯片模式转换期间减少瞬态电流摆幅的电路
公开(公告)号：US20080272820A1
公开(公告)日：2008-11-06
申请号：US12132871
申请日：2008-06-04
申请人： David William Boerstler , Eskinder Hailu , Mack Wayne Riley , Michael Fan Wang
发明人： David William Boerstler , Eskinder Hailu , Mack Wayne Riley , Michael Fan Wang
IPC分类号： H03K3/00
CPC分类号： H03K23/662 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.
摘要翻译：提供了一种方法，装置和计算机程序以减少模式转换期间的瞬态电流摆动。传统上，芯片上的瞬态电源电压波动占大部分电源。串联电感和电阻的数量通常最小化，同时在电源电压和地之间增加大的去耦电容。然而，不能实现串联电感和电阻的降低的情况。因此，为了帮助控制瞬态电流摆动，以受控的方式执行时钟频率的降低。

4. 发明授权

US07831006B2 Circuit to reduce transient current swings during mode transitions of high frequency/high power chips 有权
标题翻译：在高频/高功率芯片的模式转换期间减少瞬态电流摆幅的电路
公开(公告)号：US07831006B2
公开(公告)日：2010-11-09
申请号：US12132871
申请日：2008-06-04
申请人： David William Boerstler , Eskinder Hailu , Mack Wayne Riley , Michael Fan Wang
发明人： David William Boerstler , Eskinder Hailu , Mack Wayne Riley , Michael Fan Wang
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03K23/662 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： An apparatus is provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.
摘要翻译：提供了一种用于减少模式转换期间的瞬态电流摆动的装置。传统上，芯片上的瞬态电源电压波动占大部分电源。串联电感和电阻的数量通常最小化，同时在电源电压和地之间增加大的去耦电容。然而，不能实现串联电感和电阻的降低的情况。因此，为了帮助控制瞬态电流摆动，以受控的方式执行时钟频率的降低。

5. 发明授权

US07809974B2 Circuit to reduce power supply fluctuations in high frequency/high power circuits 有权
标题翻译：降低高频/高功率电路电源波动的电路
公开(公告)号：US07809974B2
公开(公告)日：2010-10-05
申请号：US12014830
申请日：2008-01-16
申请人： David William Boerstler , Eskinder Hailu , Mack Wayne Riley , Michael Fan Wang
发明人： David William Boerstler , Eskinder Hailu , Mack Wayne Riley , Michael Fan Wang
IPC分类号： H04L25/00
CPC分类号： G06F1/26
摘要： A circuit for transitioning clocking speeds, or frequencies, is provided. With this circuit, a clocking circuit providing a first clock signal at a first clock frequency is coupled to a counter. A comparator and a first divider are coupled to an output of the counter. The first divider outputs a second clock signal at a second clock frequency. A second divider is interposed between the clocking circuit and the counter. A processor is coupled to an output of the first divider.
摘要翻译：提供了用于转换时钟速度或频率的电路。利用该电路，以第一时钟频率提供第一时钟信号的时钟电路被耦合到计数器。比较器和第一分频器耦合到计数器的输出端。第一分频器以第二时钟频率输出第二时钟信号。在时钟电路和计数器之间插入第二分频器。处理器耦合到第一分频器的输出端。

6. 发明授权

US07430264B2 Method to reduce transient current swings during mode transitions of high frequency/high power chips 失效
标题翻译：在高频/高功率芯片的模式转换期间减少瞬态电流摆幅的方法
公开(公告)号：US07430264B2
公开(公告)日：2008-09-30
申请号：US10981154
申请日：2004-11-04
申请人： David William Boerstler , Eskinder Hailu , Mack Wayne Riley , Michael Fan Wang
发明人： David William Boerstler , Eskinder Hailu , Mack Wayne Riley , Michael Fan Wang
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03K23/662 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.
摘要翻译：提供了一种方法，装置和计算机程序以减少模式转换期间的瞬态电流摆动。传统上，芯片上的瞬态电源电压波动占大部分电源。串联电感和电阻的数量通常最小化，同时在电源电压和地之间增加大的去耦电容。然而，不能实现串联电感和电阻的降低的情况。因此，为了帮助控制瞬态电流摆动，以受控的方式执行时钟频率的降低。

7. 发明申请

US20080133957A1 Circuit to Reduce Power Supply Fluctuations in High Frequency/High Power Circuits 有权
标题翻译：降低高频/大功率电路电源波动的电路
公开(公告)号：US20080133957A1
公开(公告)日：2008-06-05
申请号：US12014830
申请日：2008-01-16
申请人： David William Boerstler , Eskinder Hailu , Mack Wayne Riley , Michael Fan Wang
发明人： David William Boerstler , Eskinder Hailu , Mack Wayne Riley , Michael Fan Wang
IPC分类号： G06F1/10
CPC分类号： G06F1/26
摘要： The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is coupled to the output of the counter. A processor means is coupled to the output of the first divider, thereby lessening current surges.
摘要翻译：本发明提供了一种用于转换时钟速度的电路。计数器耦合到计时装置。比较器耦合到计数器的输出端。第一分频器耦合到计数器的输出端。处理器装置耦合到第一分频器的输出，从而减小电流浪涌。

8. 发明授权

US07350096B2 Circuit to reduce power supply fluctuations in high frequency/ high power circuits 有权
标题翻译：降低高频/高功率电路电源波动的电路
公开(公告)号：US07350096B2
公开(公告)日：2008-03-25
申请号：US10955121
申请日：2004-09-30
申请人： David William Boerstler , Eskinder Hailu , Mack Wayne Riley , Michael Fan Wang
发明人： David William Boerstler , Eskinder Hailu , Mack Wayne Riley , Michael Fan Wang
IPC分类号： H04L25/00
CPC分类号： G06F1/26
摘要： The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is coupled to the output of the counter. A processor means is coupled to the output of the first divider, thereby lessening current surges.
摘要翻译：本发明提供了一种用于转换时钟速度的电路。计数器耦合到计时装置。比较器耦合到计数器的输出端。第一分频器耦合到计数器的输出端。处理器装置耦合到第一分频器的输出，从而减小电流浪涌。

9. 发明授权

US07747892B2 System for automatically selecting intermediate power supply voltages for intermediate level shifters 失效
标题翻译：用于自动选择中间电平转换器的中间电源电压的系统
公开(公告)号：US07747892B2
公开(公告)日：2010-06-29
申请号：US12036936
申请日：2008-02-25
申请人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： G06F1/04
CPC分类号： H03K19/017581 , H03K19/00323 , H03K19/00346
摘要： The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal. A fixed potential is configured to generate a second comparison signal. A comparator is coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.
摘要翻译：本发明提供了一种系统，包括电平移位器，其被配置为从第一功率域接收第一时钟信号，以接收计数器信号，以响应于所接收的计数器信号选择多个中间电压中的一个，并产生响应于所接收的第一时钟信号和所选择的中间电压的第二时钟信号。计数器耦合到电平移位器并被配置为接收分频时钟信号和比较结果信号，并且响应于接收到的分频时钟信号和比较结果信号产生计数器信号。分频器耦合到计数器并且被配置为接收第一时钟信号并响应于接收到的第一时钟信号产生分频时钟信号。滤波器耦合到电平移位器并且被配置为接收第二时钟信号并响应于所接收的第二时钟信号产生第一比较信号。固定电位被配置为产生第二比较信号。比较器耦合到滤波器，固定电位和计数器，并且被配置为接收第一比较信号和第二比较信号，并且响应于接收的第一比较信号和第二比较信号产生比较结果信号。

10. 发明授权

US07716516B2 Method for controlling operation of microprocessor which performs duty cycle correction process 失效
标题翻译：用于控制执行占空比校正处理的微处理器的操作的方法
公开(公告)号：US07716516B2
公开(公告)日：2010-05-11
申请号：US11471819
申请日：2006-06-21
申请人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry, Jr. , Sang Hoo Dhong
发明人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry, Jr. , Sang Hoo Dhong
IPC分类号： G06F1/04 , G06F1/24 , G06F11/00
CPC分类号： G06F1/04
摘要： A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.
摘要翻译：用于向微处理器提供电源电压的技术。在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理。在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器仍然可操作的电源电压最小化。

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