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1. 发明申请

US20050038793A1 Circular link list scheduling 有权
标题翻译：循环链表调度
公开(公告)号：US20050038793A1
公开(公告)日：2005-02-17
申请号：US10641324
申请日：2003-08-14
申请人： David Romano , Gilbert Wolrich , Donald Hooper
发明人： David Romano , Gilbert Wolrich , Donald Hooper
IPC分类号： G06F7/00 , H04L12/56
CPC分类号： H04L49/254 , H04L47/50 , H04L47/568
摘要： A scheduling mechanism to control transmission of data units, such as variable size packets or fixed size cells, to ports of a network device such as a switching fabric system. The scheduling mechanism maintains scheduling data structures, including an array storing information for available queues of ports and circular buffers representing nonempty port queues of the available port queues according to classes of service. The scheduling mechanism uses the data structures to make scheduling decisions concerning the scheduling of data units in the nonempty port queues for transmission to the ports.
摘要翻译：控制诸如可变大小分组或固定大小小区之类的数据单元的传输到诸如交换结构系统的网络设备的端口的调度机制。调度机制维护调度数据结构，包括根据服务类别存储可用队列的信息和表示可用端口队列的非空端口队列的循环缓冲区。调度机制使用数据结构来做出关于非空端口队列中的数据单元的调度的调度决定，以传送到端口。

2. 发明申请

US20050018601A1 Traffic management 审中-公开
标题翻译：交通管理
公开(公告)号：US20050018601A1
公开(公告)日：2005-01-27
申请号：US10612552
申请日：2003-07-01
申请人： Suresh Kalkunte , Hugh Wilkinson , Gilbert Wolrich , Mark Rosenbluth , Donald Hooper
发明人： Suresh Kalkunte , Hugh Wilkinson , Gilbert Wolrich , Mark Rosenbluth , Donald Hooper
IPC分类号： H04L12/56 , H04Q11/04 , H04L1/00
CPC分类号： H04L12/5601 , H04L2012/561 , H04L2012/5636 , H04L2012/5679
摘要： In general, in one aspect, the disclosure describes a system to process packets received over a network. The system includes a receive process of at least one thread of a network processor to receive data of packets belonging to different flows. The system also includes a transmit process of at least one thread to transmit packets received by the receive process. A scheduler process of at least one thread populates at least one schedule of flow service based, at least in part, on quality of service characteristics associated with the different flows. The schedule identifies different flow candidates for service. The system also includes a shaper process of at least one thread to select from the candidate flows for service from the at least one schedule.
摘要翻译：一般来说，一方面，本公开描述了一种处理通过网络接收的分组的系统。该系统包括网络处理器的至少一个线程的接收处理，以接收属于不同流的分组的数据。系统还包括至少一个线程的发送过程，以发送由接收过程接收的分组。至少部分地基于与不同流相关联的服务质量特征，至少一个线程的调度器过程填充至少一个流服务调度。计划确定不同的候选候选人的服务。该系统还包括至少一个线程的整形过程，以从候选流中选择来自至少一个调度的服务。

3. 发明授权

US07111296B2 Thread signaling in multi-threaded processor 失效
标题翻译：线程信令在多线程处理器中
公开(公告)号：US07111296B2
公开(公告)日：2006-09-19
申请号：US10615280
申请日：2003-07-08
申请人： Gilbert Wolrich , Debra Bernstein , Donald Hooper , Matthew J. Adiletta , William Wheeler
发明人： Gilbert Wolrich , Debra Bernstein , Donald Hooper , Matthew J. Adiletta , William Wheeler
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个程序线程的多个微启动器。处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用引用是读取引用或写入引用。还描述了用于分组处理的程序线程通信方案。

4. 发明申请

US20050039182A1 Phasing for a multi-threaded network processor 有权
标题翻译：分阶段的多线程网络处理器
公开(公告)号：US20050039182A1
公开(公告)日：2005-02-17
申请号：US10642053
申请日：2003-08-14
申请人： Donald Hooper , Mark Rosenbluth , Debra Bernstein , Michael Fallon , Sanjeev Jain , Gilbert Wolrich
发明人： Donald Hooper , Mark Rosenbluth , Debra Bernstein , Michael Fallon , Sanjeev Jain , Gilbert Wolrich
IPC分类号： G06F9/46
CPC分类号： G06F9/5038 , G06F2209/5018 , H04L69/12
摘要： A method of and apparatus for associating units of data with threads of a multi-threaded processor for processing, and enabling each thread to perform processing for at least two of the data units during a thread execution period. The thread execution period is divided among phases, and each of the data units processed by a thread is processed by a different one of the phases.
摘要翻译：一种用于将数据单元与多线程处理器的线程相关联以用于处理的方法和装置，并且使得每个线程能够在线程执行周期期间对至少两个数据单元执行处理。线程执行周期在各个阶段之间分割，线程处理的每个数据单元都由不同的相位进行处理。

5. 发明申请

US20050038964A1 Folding for a multi-threaded network processor 有权
标题翻译：折叠为多线程网络处理器
公开(公告)号：US20050038964A1
公开(公告)日：2005-02-17
申请号：US10642061
申请日：2003-08-14
申请人： Donald Hooper , Hugh Wilkinson , Mark Rosenbluth , Debra Bernstein , Michael Fallon , Sanjeev Jain , Myles Wilde , Gilbert Wolrich
发明人： Donald Hooper , Hugh Wilkinson , Mark Rosenbluth , Debra Bernstein , Michael Fallon , Sanjeev Jain , Myles Wilde , Gilbert Wolrich
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0842 , G06F12/0804
摘要： A mechanism to process units of data associated with a dependent data stream using different threads of execution and a common data structure in memory. Accessing the common data structure in memory for the processing uses a single read operation and a single write operation. The folding of multiple read-modify-write memory operations in such a manner for multiple multi-threaded stages of processing includes controlling a first stage, which operates on the same data unit as a second stage to pass context state information to the second stage for coherency.
摘要翻译：使用不同的执行线程和存储器中的公共数据结构来处理与依赖数据流相关联的数据单元的机制。访问存储器中用于处理的公共数据结构使用单个读取操作和单个写入操作。以多个多线程处理阶段的方式折叠多个读 - 修改 - 写存储器操作包括控制第一级，其在与第二级相同的数据单元上操作以将上下文状态信息传递到第二级，用于一致性

6. 发明授权

US06625654B1 Thread signaling in multi-threaded network processor 失效
标题翻译：线程信令在多线程网络处理器中
公开(公告)号：US06625654B1
公开(公告)日：2003-09-23
申请号：US09473799
申请日：1999-12-28
申请人： Gilbert Wolrich , Debra Bernstein , Donald Hooper , Matthew J. Adiletta , William Wheeler
发明人： Gilbert Wolrich , Debra Bernstein , Donald Hooper , Matthew J. Adiletta , William Wheeler
IPC分类号： G06F1516
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed than even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个程序线程的多个微启动器。该处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是指向甚至是存储体还是奇数存储器存储器排序存储器引用;以及第二存储器控制器，其基于存储器引用来优化存储器引用被读取引用或写入引用。还描述了用于分组处理的程序线程通信方案。

7. 发明授权

US07191309B1 Double shift instruction for micro engine used in multithreaded parallel processor architecture 有权
标题翻译：用于多线程并行处理器架构的微型引擎的双移位指令
公开(公告)号：US07191309B1
公开(公告)日：2007-03-13
申请号：US10070006
申请日：2000-08-31
申请人： Gilbert Wolrich , Matthew I. Adiletta , William Wheeler , Debra Bernstein , Donald Hooper
发明人： Gilbert Wolrich , Matthew I. Adiletta , William Wheeler , Debra Bernstein , Donald Hooper
IPC分类号： G06F9/315 , G06F9/32
CPC分类号： G06F9/30032 , G06F9/32
摘要： A method of operating a processor includes concatenating a first word and a second word to produce an intermediate result, shifting the intermediate result by a specified shift amount and storing the shifted intermediate result in a third word, to create an address.
摘要翻译：一种操作处理器的方法包括连接第一字和第二字以产生中间结果，将中间结果移位指定的移位量并将移位的中间结果存储在第三个字中，以创建一个地址。

8. 发明申请

US20060156303A1 Multi-threaded sequenced receive for fast network port stream of packets 有权
标题翻译：多线程排序接收快速网络端口流数据包
公开(公告)号：US20060156303A1
公开(公告)日：2006-07-13
申请号：US11239547
申请日：2005-09-28
申请人： Donald Hooper , Matthew Adiletta , Gilbert Wolrich
发明人： Donald Hooper , Matthew Adiletta , Gilbert Wolrich
IPC分类号： G06F9/46
CPC分类号： G06F9/546 , G06F9/3851 , G06F9/3885 , G06F9/485 , G06F9/4881 , G06F9/544
摘要： A method of processing network data in a network processor includes using three or more threads to process a beginning portion, a middle portion, and an end portion of data packet. The first thread processes the beginning portion; one or more middle threads process the middle portion, and a last thread processes the end portion. First information is indirectly passed from the first thread to the last thread via a first buffer with the middle threads progressively updating the first information. Second information is directly passed from the first thread to the last thread via a second buffer.
摘要翻译：一种在网络处理器中处理网络数据的方法包括使用三个或更多个线程来处理数据分组的开始部分，中间部分和结束部分。第一个线程处理起始部分; 一个或多个中间线程处理中间部分，最后一个线程处理端部。第一个信息通过第一个缓冲区从第一个线程间接传递到最后一个线程，中间线程逐渐更新第一个信息。第二个信息通过第二个缓冲区从第一个线程直接传递到最后一个线程。

9. 发明申请

US20060150165A1 Virtual microengine systems and methods 审中-公开
标题翻译：虚拟微型发动机系统和方法
公开(公告)号：US20060150165A1
公开(公告)日：2006-07-06
申请号：US11027785
申请日：2004-12-30
申请人： Donald Hooper , Prashant Chandra , James Guilford , Mark Rosenbluth
发明人： Donald Hooper , Prashant Chandra , James Guilford , Mark Rosenbluth
IPC分类号： G06F9/45
CPC分类号： G06F9/455
摘要： Systems and methods are disclosed for supporting virtual microengines in a multithreaded processor, such as a microengine running on a network processor. In one embodiment code is written for execution by a plurality of virtual microengines. The code is than compiled and linked for execution on a physical microengine, at which time the physical microengine's threads are assigned to thread groups corresponding to the virtual microengines. Internal next neighbor rings are allocated within the physical microengine to facilitate communication between the thread groups. The code can then be loaded onto the physical microengine and executed, with each thread group executing the code written for its corresponding virtual microengine.
摘要翻译：公开了用于在多线程处理器中支持虚拟微引擎的系统和方法，诸如在网络处理器上运行的微型引擎。在一个实施例中，代码被写入以由多个虚拟微引擎执行。代码被编译和链接以在物理微引擎上执行，此时物理微引擎的线程被分配给对应于虚拟微引擎的线程组。内部下一个邻居环在物理微引擎内分配，以促进线程组之间的通信。然后可以将代码加载到物理微引擎上并执行，每个线程组执行为其相应的虚拟微引擎编写的代码。

10. 发明申请

US20050288917A1 Packet dataflow packet trace graphics user interface 失效
标题翻译：数据包数据流跟踪图形用户界面
公开(公告)号：US20050288917A1
公开(公告)日：2005-12-29
申请号：US10877922
申请日：2004-06-25
申请人： Donald Hooper , Eric Walker , Dennis Rivard , Mark Rosenbluth
发明人： Donald Hooper , Eric Walker , Dennis Rivard , Mark Rosenbluth
IPC分类号： G06F13/10
CPC分类号： G06F11/3664 , G06F11/3636
摘要： A debugger tool that enables a user to perform packet-centric debugging in a network processor simulation environment is presented.
摘要翻译：提出了一种使用户能够在网络处理器仿真环境中执行以分组为中心的调试的调试工具。

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