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1. 发明授权

US4892753A Process for PECVD of silicon oxide using TEOS decomposition 失效
公开(公告)号：US4892753A
公开(公告)日：1990-01-09
申请号：US262993
申请日：1988-10-26
申请人： David N. Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
发明人： David N. Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
IPC分类号： C23C16/40 , C23C16/44 , C23C16/455 , C23C16/509 , C23C16/54 , H01L21/314 , H01L21/316
CPC分类号： C23C16/45565 , C23C16/402 , C23C16/455 , C23C16/45521 , C23C16/5096 , C23C16/54 , H01J37/32082 , H01J37/3244 , H01L21/31604
摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

2. 发明授权

US4872947A CVD of silicon oxide using TEOS decomposition and in-situ planarization process 失效
标题翻译：使用TEOS分解和原位平面化处理的氧化硅CVD
公开(公告)号：US4872947A
公开(公告)日：1989-10-10
申请号：US262992
申请日：1988-10-26
申请人： David N. Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
发明人： David N. Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
IPC分类号： C23C16/40 , C23C16/44 , C23C16/455 , C23C16/509 , C23C16/54 , H01L21/314 , H01L21/316
CPC分类号： C23C16/45565 , C23C16/402 , C23C16/455 , C23C16/45521 , C23C16/5096 , C23C16/54 , H01J37/32082 , H01J37/3244 , H01L21/31604
摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either along or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.
摘要翻译：公开了一种高压，高通量，单晶片，半导体处理反应器，其能够通过溅射单独地或作为一部分的溅射进行热CVD，等离子体增强CVD，等离子体辅助回蚀，等离子体自清洁和沉积形貌修饰原位多步处理。还公开了用于形成高度保形二氧化硅层的低温CVD工艺。该过程使用非常高的室压和低温，以及TEOS和臭氧反应物。低温CVD二氧化硅沉积步骤特别可用于平坦化下面的阶梯介电层，或者沿着或结合随后的各向同性蚀刻。用于形成平坦化的二氧化硅层的优选的原位多步骤方法使用（1）在低温和高压下高速二氧化硅沉积，随后（2）也在高压下沉积保形二氧化硅层，以及低温，随后（3）高速各向同性蚀刻，优选在低温和高压下，在用于两个氧化物沉积步骤的相同反应器中。公开了用于不同应用的步骤的各种组合，优选的反应器自清洁步骤也是如此。

3. 发明授权

US5362526A Plasma-enhanced CVD process using TEOS for depositing silicon oxide 失效
公开(公告)号：US5362526A
公开(公告)日：1994-11-08
申请号：US645999
申请日：1991-01-23
申请人： David N. Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
发明人： David N. Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
IPC分类号： C23C16/48 , C23C16/04 , C23C16/40 , C23C16/42 , C23C16/44 , C23C16/455 , C23C16/46 , C23C16/50 , C23C16/509 , C23C16/54 , C23F4/00 , C30B25/14 , H01L21/205 , H01L21/302 , H01L21/3065 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/683 , B05D3/06
CPC分类号： C23C16/45565 , C23C16/402 , C23C16/455 , C23C16/45521 , C23C16/5096 , C23C16/54 , H01J37/32082 , H01J37/3244 , H01L21/31604
摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

4. 发明授权

US5000113A Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process 失效
标题翻译：热CVD / PECVD反应器和用于二氧化硅的热化学气相沉积和原位多步平面化处理
公开(公告)号：US5000113A
公开(公告)日：1991-03-19
申请号：US944492
申请日：1986-12-19
申请人： David N. Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
发明人： David N. Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
IPC分类号： C23C16/48 , C23C16/04 , C23C16/40 , C23C16/42 , C23C16/44 , C23C16/455 , C23C16/46 , C23C16/50 , C23C16/509 , C23C16/54 , C23F4/00 , C30B25/14 , H01L21/205 , H01L21/302 , H01L21/3065 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/683
CPC分类号： C23C16/45565 , C23C16/402 , C23C16/455 , C23C16/45521 , C23C16/5096 , C23C16/54 , H01J37/32082 , H01J37/3244 , H01L21/31604
摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures.

5. 发明授权

US06167834A Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process 失效
公开(公告)号：US06167834A
公开(公告)日：2001-01-02
申请号：US07928642
申请日：1992-08-13
申请人： David Nin-Kou Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
发明人： David Nin-Kou Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
IPC分类号： C23C1600
CPC分类号： C23C16/45565 , C23C16/402 , C23C16/455 , C23C16/45521 , C23C16/5096 , C23C16/54 , H01J37/32082 , H01J37/3244 , H01L21/31604
摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, the TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

6. 发明授权

US5354715A Thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process 失效
标题翻译：二氧化硅的热化学气相沉积和原位多步平面化工艺
公开(公告)号：US5354715A
公开(公告)日：1994-10-11
申请号：US861719
申请日：1992-04-01
申请人： David N-K. Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
发明人： David N-K. Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
IPC分类号： C23C16/48 , C23C16/04 , C23C16/40 , C23C16/42 , C23C16/44 , C23C16/455 , C23C16/46 , C23C16/50 , C23C16/509 , C23C16/54 , C23F4/00 , C30B25/14 , H01L21/205 , H01L21/302 , H01L21/3065 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/683 , H01L21/00 , H01L21/02
CPC分类号： C23C16/45565 , C23C16/402 , C23C16/455 , C23C16/45521 , C23C16/5096 , C23C16/54 , H01J37/32082 , H01J37/3244 , H01L21/31604
摘要： A high pressure, high throughout, single wafer semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature process for forming a highly conformal layer of silicon dioxide from a plasma of TEOS, oxygen and ozone is also disclosed. This layer can be planarized using an etchback process. Silicon oxide deposition and etchback can be carried out sequentially in the reactor.
摘要翻译：公开了一种高压，高整体的单晶片半导体处理反应器，其能够通过溅射单独地或作为部分的，通过溅射进行热CVD，等离子体增强CVD，等离子体辅助回蚀，等离子体自清洁和沉积形貌修饰，原位多步处理。该反应器在包括非常高的压力的宽范围的压力下提供均匀的加工。还公开了一种用于从TEOS，氧气和臭氧的等离子体形成高度保形二氧化硅层的低温工艺。该层可以使用回蚀工艺进行平面化。氧化硅沉积和回蚀可以在反应器中顺序进行。

7. 发明授权

US5871811A Method for protecting against deposition on a selected region of a substrate 失效
标题翻译：防止沉积在基底的选定区域上的方法
公开(公告)号：US5871811A
公开(公告)日：1999-02-16
申请号：US477536
申请日：1995-06-07
申请人： David Nin-Kou Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
发明人： David Nin-Kou Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
IPC分类号： C23C16/04 , C23C16/40 , C23C16/44 , C23C16/455 , C23C16/509 , C23C16/54 , H01L21/314 , H01L21/316 , C23C16/00
CPC分类号： C23C16/45565 , C23C16/402 , C23C16/455 , C23C16/45521 , C23C16/5096 , C23C16/54 , H01J37/32082 , H01J37/3244 , H01L21/31604
摘要： A method for protecting a selected area of a substrate against deposition on the selected area. The method includes the steps of flowing a process gas into a substrate processing chamber and flowing a purge gas to the selected area of the substrate to prevent the process gas from contacting the selected area or minimize contact between the process gas and the selected area. In various embodiments the selected area is a backside periphery of the substrate or the edge of the substrate. Also in these embodiments, the process gas is flowed into a deposition zone in order to deposit a thin film layer over an upper surface of the substrate, and a flow of the process and purge gas is established such that the process gas flows radically across the upper surface of the substrate, combines with the purge gas near an edge of the substrate and exits the processing chamber through an exhaust system.
摘要翻译：一种用于保护衬底的选定区域以防止沉积在所选区域上的方法。该方法包括以下步骤：将工艺气体流入衬底处理室并将吹扫气体流动到衬底的选定区域，以防止工艺气体接触选定区域或最小化工艺气体与所选区域之间的接触。在各种实施例中，所选择的区域是衬底的背面周边或衬底的边缘。同样在这些实施方案中，工艺气体流入沉积区，以便在衬底的上表面上沉积薄膜层，并建立工艺和吹扫气体的流动，使得工艺气体基本上流过基板的上表面与基板边缘附近的吹扫气体结合，并通过排气系统离开处理室。

8. 发明授权

US5755886A Apparatus for preventing deposition gases from contacting a selected region of a substrate during deposition processing 失效
标题翻译：用于在沉积处理期间防止沉积气体接触衬底的选定区域的装置
公开(公告)号：US5755886A
公开(公告)日：1998-05-26
申请号：US483750
申请日：1995-06-07
申请人： David Nin-Kou Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
发明人： David Nin-Kou Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
IPC分类号： C23C16/04 , C23C16/40 , C23C16/44 , C23C16/455 , C23C16/509 , C23C16/54 , H01L21/314 , H01L21/316 , C23C16/00
CPC分类号： C23C16/45565 , C23C16/402 , C23C16/455 , C23C16/45521 , C23C16/5096 , C23C16/54 , H01J37/32082 , H01J37/3244 , H01L21/31604
摘要： A substrate processing reactor capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning and other substrate processing operations all of which can either be performed separately or as part of in-situ multiple step processing. The reactor incorporates a uniform radial gas pumping system which enables uniform reactant gas flow across the wafer. Also included are upper and lower purge gas dispersers. The upper purge gas disperser directs purge gas flow downwardly toward the periphery of the wafer while the lower gas disperser directs purge gas across the backside of the wafer. The radial pumping gas system and purge gas dispersers sweep radially away from the wafer to prevent deposition external to the wafer and keep the chamber clean.
摘要翻译：能够进行热CVD，等离子体增强CVD，等离子体辅助回蚀，等离子体自清洁和其它基板处理操作的基板处理反应器，所有这些都可以单独进行或作为原位多步骤处理的一部分进行。该反应器包含均匀的径向气体泵送系统，其能够跨过晶片均匀的反应气体流动。还包括上部和下部吹扫气体分散器。上部吹扫气体分散器将吹扫气体向下流向晶片的周边，而下部气体分散器引导吹扫气体穿过晶片的背面。径向泵送气体系统和吹扫气体分散器径向扫掠离开晶片，以防止晶片外部沉积并保持室清洁。

9. 再颁专利

USRE36623E Process for PECVD of silicon oxide using TEOS decomposition 失效
公开(公告)号：USRE36623E
公开(公告)日：2000-03-21
申请号：US752972
申请日：1996-12-02
申请人： David Nin-Kou Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
发明人： David Nin-Kou Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
IPC分类号： C23C16/40 , C23C16/44 , C23C16/455 , C23C16/509 , C23C16/54 , H01L21/314 , H01L21/316 , H05H1/24
CPC分类号： C23C16/45565 , C23C16/402 , C23C16/455 , C23C16/45521 , C23C16/5096 , C23C16/54 , H01J37/32082 , H01J37/3244 , H01L21/31604
摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surface. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the sane reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

10. 发明授权

US08821637B2 Temperature controlled lid assembly for tungsten nitride deposition 有权
标题翻译：用于氮化钨沉积的温度控制盖组件
公开(公告)号：US08821637B2
公开(公告)日：2014-09-02
申请号：US12021825
申请日：2008-01-29
申请人： Avgerinos V. Gelatos , Sang-Hyeob Lee , Xiaoxiong Yuan , Salvador P. Umotoy , Yu Chang , Gwo-Chuan Tzu , Emily Renuart , Jing Lin , Wing-Cheong Lai , Sang Q. Le
发明人： Avgerinos V. Gelatos , Sang-Hyeob Lee , Xiaoxiong Yuan , Salvador P. Umotoy , Yu Chang , Gwo-Chuan Tzu , Emily Renuart , Jing Lin , Wing-Cheong Lai , Sang Q. Le
IPC分类号： C23C16/455 , C23C16/00
CPC分类号： C23C16/14 , C23C16/34 , C23C16/4401 , C23C16/4411 , C23C16/45512 , C23C16/45523
摘要： Embodiments of the invention provide apparatuses for vapor depositing tungsten-containing materials, such as metallic tungsten and tungsten nitride. In one embodiment, a processing chamber is provided which includes a lid assembly containing a lid plate, a showerhead, a mixing cavity, a distribution cavity, and a resistive heating element contained within the lid plate. In one example, the resistive heating element is configured to provide the lid plate at a temperature within a range from about 120° C. to about 180° C., preferably, from about 140° C. to about 160° C., more preferably, from about 145° C. to about 155° C. The mixing cavity may be in fluid communication with a tungsten precursor source containing tungsten hexafluoride and a nitrogen precursor source containing ammonia. In some embodiments, a single processing chamber may be used to deposit metallic tungsten and tungsten nitride materials by CVD processes.
摘要翻译：本发明的实施例提供了用于气相沉积含钨材料如金属钨和氮化钨的装置。在一个实施例中，提供了一种处理室，其包括盖子组件，该盖子组件包含盖板，喷头，混合腔，分配腔和容纳在盖板内的电阻加热元件。在一个示例中，电阻加热元件被配置成将盖板设置在约120℃至约180℃，优选约140℃至约160℃的温度范围内，更多优选约145℃至约155℃。混合腔可与含有六氟化钨的钨前体源和含氨的氮前体源流体连通。在一些实施例中，单个处理室可用于通过CVD工艺沉积金属钨和氮化钨材料。

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