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1. 发明授权

US06532553B1 Debugging data processing systems 有权
标题翻译：调试数据处理系统
公开(公告)号：US06532553B1
公开(公告)日：2003-03-11
申请号：US09407846
申请日：1999-09-29
申请人： David John Gwilt , Andrew Christopher Rose , Peter Guy Middleton , David Michael Bull
发明人： David John Gwilt , Andrew Christopher Rose , Peter Guy Middleton , David Michael Bull
IPC分类号： H02H305
CPC分类号： G06F11/3636 , G06F9/30003 , G06F9/3005
摘要： A data processing system is provided having a main processor 4 and a coprocessor 26. When in a debug mode, the main processor 4 and the coprocessor 26 are supplied with different instructions. The coprocessor 26 is supplied with a coprocessor debug data generation instruction (MCR) whilst the main processor 4 is supplied with a main processor data capture instruction (LDR). The coprocessor 26 responds to the MCR instruction by controlling debug data representing state of the data processing apparatus 2 to be placed upon a data bus 24 from where it is read by the main processor 4 under control of the LDR instruction.
摘要翻译：提供了具有主处理器4和协处理器26的数据处理系统。当处于调试模式时，向主处理器4和协处理器26提供不同的指令。协处理器26被提供有协处理器调试数据生成指令（MCR），而主处理器4被提供有主处理器数据捕获指令（LDR）。协处理器26通过控制表示数据处理装置2的状态的调试数据来响应MCR指令，数据处理装置2将被放置在数据总线24上，从LDR指令的控制下由主处理器4读取数据总线24。

2. 发明授权

US06172530B2 Decoder for generating N output signals from two or more precharged input signals 失效
标题翻译：用于从两个或多个预充电输入信号产生N个输出信号的解码器
公开(公告)号：US06172530B2
公开(公告)日：2001-01-09
申请号：US09335696
申请日：1999-06-18
申请人： David Michael Bull , Andrew Christopher Rose
发明人： David Michael Bull , Andrew Christopher Rose
IPC分类号： G11C800
CPC分类号： G11C8/00
摘要： A decoder is provided for generating N output signals, the decoder comprising a precharged gate structure arranged to receive two or more input signals and to generate N intermediate signals. In a precharge phase, the precharged gate structure is arranged to output the N intermediate signals at a first logic value, and in an evaluate phase the precharged gate structure is arranged to maintain a first intermediate signal at the first logic value, and to cause all other intermediate signals to transition to a second logic value. Further, self-timed logic is provided for receiving the N intermediate signals, and for generating the N output signals, the self-timed logic being arranged, during the precharge phase, to generate the N output signals at the second logic value, and during the evaluate phase to cause a first output signal corresponding to the first intermediate signal to transition to the first logic value. The self-timed logic is further arranged to generate each output signal from the corresponding intermediate signal as qualified to predetermined other intermediate signal, such that the transition of the first output signal to the first logic value is delayed by a first predetermined time after the predetermined other intermediate signal has transitioned to the second logic value.
摘要翻译：提供了用于产生N个输出信号的解码器，该解码器包括预充电栅极结构，其被布置为接收两个或更多个输入信号并产生N个中间信号。在预充电阶段，预充电栅极结构被布置为以第一逻辑值输出N个中间信号，并且在评估阶段中，预充电栅结构被布置成将第一中间信号保持在第一逻辑值，并且使所有其他中间信号转换到第二逻辑值。此外，提供自定时逻辑用于接收N个中间信号，并且为了产生N个输出信号，在预充电阶段期间，自定时逻辑被布置为以第二逻辑值生成N个输出信号，并且在所述评估阶段使得对应于所述第一中间信号的第一输出信号转变到所述第一逻辑值。自定时逻辑还被布置为从对应的中间信号产生符合预定的其他中间信号的每个输出信号，使得第一输出信号到第一逻辑值的转变在预定的第一预定时间后延迟第一预定时间其他中间信号已经转换到第二逻辑值。

3. 发明授权

US09519538B2 Error recovery following speculative execution with an instruction processing pipeline 有权
标题翻译：使用指令处理流水线进行推测执行后出错恢复
公开(公告)号：US09519538B2
公开(公告)日：2016-12-13
申请号：US13067510
申请日：2011-06-06
申请人： Emre Özer , Shidhartha Das , David Michael Bull
发明人： Emre Özer , Shidhartha Das , David Michael Bull
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F11/07 , G06F9/38
CPC分类号： G06F11/0793 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3867 , G06F11/0721
摘要： An instruction processing pipeline having error detection and error recovery circuitry associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need be flushed from the instruction pipeline. The instruction pipeline may additionally/alternatively be provided with more than one main storage element associated with each signal value with these main storage elements used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element to properly capture the signal value corresponding to the following program instruction.
摘要翻译：具有与一个或多个流水线级相关联的错误检测和错误恢复电路的指令处理流水线。如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。部分错误恢复可能是从指令流水线中刷新上游程序指令。当多线程时，只有来自包括作为错误恢复的结果已经丢失的指令的线程的那些指令需要从指令流水线中刷新。指令流水线可以另外/替代地设置有与每个信号值相关联的多于一个主存储元件，这些主存储元件以交替方式使用，使得如果信号值被错误地捕获并且需要被修复，则仍然存在可用主存储元件来适当地捕获与以下程序指令对应的信号值。

4. 发明授权

US08640008B2 Error recovery in a data processing apparatus 有权
标题翻译：数据处理设备中的错误恢复
公开(公告)号：US08640008B2
公开(公告)日：2014-01-28
申请号：US13336428
申请日：2011-12-23
申请人： Guillaume Schon , Luca Scalabrino , Frederic Claude Marie Piry , David Michael Bull
发明人： Guillaume Schon , Luca Scalabrino , Frederic Claude Marie Piry , David Michael Bull
IPC分类号： H03M13/00
CPC分类号： G06F11/1407 , G06F11/1497
摘要： A data processing apparatus has error detection units each configured to generate an error signal if a first and second sample of a signal associated with execution of an instruction differ. Error value generation circuitry generates an error value showing if any of the error detection units have generated the error signal. Error value stabilisation circuitry performs a stabilisation procedure comprising re-sampling the error value to remove metastability. Error recovery circuitry initiates re-execution of the instruction if the error value is asserted. Count circuitry holds a counter value in association with the error value, the counter value set to a predetermined value when the error value is generated and decremented each time the error value is re-sampled prior to reaching the error value stabilisation circuitry. The error value bypasses the stabilisation procedure if the counter value is zero before the error value reaches the error value stabilisation circuitry.
摘要翻译：数据处理装置具有错误检测单元，每个错误检测单元被配置为如果与指令的执行相关联的信号的第一和第二采样不同，则生成错误信号。错误值产生电路产生一个错误值，显示任何错误检测单元是否产生了错误信号。误差值稳定电路执行稳定程序，包括重新采样误差值以消除亚稳态。错误恢复电路如果错误值被确认则启动指令的重新执行。计数电路与错误值相关联地保持计数器值，当误差值被产生并且每当在到达误差值稳定电路之前重新采样误差值时递减，计数器值被设置为预定值。如果在错误值到达故障值稳定电路之前计数器值为零，则误差值会绕过稳定程序。

5. 发明授权

US08621272B2 Integrated circuit with error repair and fault tolerance 有权
公开(公告)号：US08621272B2
公开(公告)日：2013-12-31
申请号：US12735339
申请日：2008-12-29
申请人： Shidhartha Das , David Michael Bull , Emre Ozer
发明人： Shidhartha Das , David Michael Bull , Emre Ozer
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G01R31/31816 , G06F11/1076 , G06F11/1608
摘要： An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

6. 发明申请

US20120131313A1 Error recovery following speculative execution with an instruction processing pipeline 有权
标题翻译：使用指令处理流水线进行推测执行后出错恢复
公开(公告)号：US20120131313A1
公开(公告)日：2012-05-24
申请号：US13067510
申请日：2011-06-06
申请人： Emre Ozer , Shidhartha Das , David Michael Bull
发明人： Emre Ozer , Shidhartha Das , David Michael Bull
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F11/0793 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3867 , G06F11/0721
摘要： An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline 6. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need to be flushed from the instruction pipeline 6. Instruction can also be selected for flushing in dependence upon characteristics such as privileged level, number of dependent instructions etc. The instruction pipeline may additionally/alternatively be provided with more than one main storage element 26, 28 associated with each signal value with these main storage elements 26, 28 being used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element 26, 28 to properly capture the signal value corresponding to the following program instruction. In this way flushes can be avoided.
摘要翻译：提供了指令处理流水线6。这具有与一个或多个流水线级相关联的错误检测和错误恢复电路20。如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。错误恢复的一部分可能是从指令流水线6冲洗上游程序指令。当多线程时，只有来自包括作为错误恢复的结果已经丢失的指令的线程的那些指令需要从指令中刷新流水线6.也可以根据诸如特权级别，依赖指令数量等特征来选择刷新指令。指令流水线可以另外地或替代地设置有多个主存储元件26,28，其与每个信号值相关联，这些主存储元件26,28以交替的方式使用，使得如果信号值被错误地捕获并且需要修复，则仍然可以使用主存储元件26,28来适当地捕获对应于以下的信号值程序指令。这样可以避免冲洗。

7. 发明授权

US08185812B2 Single event upset error detection within an integrated circuit 有权
标题翻译：集成电路内的单事件镦粗错误检测
公开(公告)号：US08185812B2
公开(公告)日：2012-05-22
申请号：US11636716
申请日：2006-12-11
申请人： Shidhartha Das , David Theodore Blaauw , David Michael Bull
发明人： Shidhartha Das , David Theodore Blaauw , David Michael Bull
IPC分类号： G06F11/00
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8. Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These single event upset errors can be detected by detecting a transition in the stored value stored by the sequential storage elements 8 occurring outside of a valid transition period associated with that sequential storage element 8.
摘要翻译：集成电路2包括逻辑电路10和顺序存储元件8.逻辑电路10和顺序存储元件8都可能经受粒子撞击，从而引起单事件失真错误。可以通过检测在与该顺序存储元件8相关联的有效过渡时段之外发生的顺序存储元件8存储的存储值中的转变来检测这些单事件中断错误。

8. 发明授权

US07895469B2 Integrated circuit using speculative execution 有权
标题翻译：集成电路采用推测执行
公开(公告)号：US07895469B2
公开(公告)日：2011-02-22
申请号：US12285796
申请日：2008-10-14
申请人： Emre Özer , David Michael Bull , Shidhartha Das
发明人： Emre Özer , David Michael Bull , Shidhartha Das
IPC分类号： G06F11/00
CPC分类号： G06F9/3842 , G06F9/3861 , G06F9/3869
摘要： An integrated circuit 2 is provided with a plurality of pipeline stages 10. These pipeline stages 10 have speculative processing control circuitry 12 which permits speculative processing in downstream pipeline stages and triggers a first error recovery operation (partial pipeline flushing) if such speculative processing is determined to be based upon an error. The pipeline stage 10 further includes speculative error detecting circuitry 14 which generates a prediction nc regarding whether or not the processing circuitry 18 will produce an error. This prediction is used to trigger a second error recovery operation (partial pipeline stall). This second error recovery operation has a lower performance penalty than the first error recovery operation.
摘要翻译：集成电路2设置有多个流水线级10.这些流水线级10具有推测性处理控制电路12，其允许下游流水线级的推测性处理，并且如果确定了这种推测性处理，则触发第一错误恢复操作（部分流水线冲洗）基于错误。流水线级10还包括推测性错误检测电路14，其产生关于处理电路18是否将产生错误的预测nc。该预测用于触发第二次错误恢复操作（部分流水线停止）。该第二错误恢复操作具有比第一错误恢复操作更低的性能损失。

9. 发明申请

US20100064287A1 Scheduling control within a data processing system 有权
标题翻译：数据处理系统内的调度控制
公开(公告)号：US20100064287A1
公开(公告)日：2010-03-11
申请号：US12458699
申请日：2009-07-21
申请人： David Michael Bull , Emre Ozer , Shidhartha Das
发明人： David Michael Bull , Emre Ozer , Shidhartha Das
IPC分类号： G06F9/30 , G06F11/07 , G06F9/46
CPC分类号： G06F9/3836 , G06F9/3861 , G06F9/3869 , G06F9/3891 , G06F11/004 , G06F11/1405
摘要： A processor 2 is responsive to a stream of program instructions to issue program instructions under control of scheduling circuitry 6 to respective execution units 24 for execution. The execution units 24 can include error detecting circuitry 32 for detecting a change in an output signal which occurs after the output signal has latched and during an error detecting period following the latching of the output signal. The scheduling circuitry 6 is arranged so as to suppress issue of program instructions to an execution unit 24 having such error detecting circuitry 32 on consecutive processing cycles.
摘要翻译：处理器2响应于程序指令流，以在调度电路6的控制下发出程序指令，以执行相应的执行单元24。执行单元24可以包括用于检测在输出信号被锁存之后和在锁存输出信号之后的错误检测周期期间发生的输出信号的变化的错误检测电路32。调度电路6被布置为在连续的处理周期中抑制对具有这种错误检测电路32的执行单元24的程序指令的发出。

10. 发明申请

US20090282281A1 Low power, high reliability specific compound functional units 有权
标题翻译：低功耗，高可靠性的复合功能单元
公开(公告)号：US20090282281A1
公开(公告)日：2009-11-12
申请号：US12285373
申请日：2008-10-02
申请人： David Michael Bull , Ganesh Suryanarayan Dasika
发明人： David Michael Bull , Ganesh Suryanarayan Dasika
IPC分类号： G06F11/07
CPC分类号： G06F11/004 , G06F9/3869 , G06F11/0793
摘要： To prevent short path errors from occurring in systems having error detection and recovery mechanisms, functional elements are combined to form compound functional units comprising at least two evaluation stages, each evaluation stage including at least one functional element. At least one functional element includes error detection/recovery circuitry. The flow of input values to the first evaluation stage in the compound functional unit is controlled so that the input values are changed at most every second clock cycle.
摘要翻译：为了防止在具有错误检测和恢复机制的系统中发生短路径错误，将功能元件组合以形成包括至少两个评估阶段的复合功能单元，每个评估阶段包括至少一个功能元件。至少一个功能元件包括错误检测/恢复电路。对复合功能单元中的第一评估阶段的输入值的流程进行控制，使得输入值最多每隔一个时钟周期改变。

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