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1. 发明授权

US09311228B2 Power reduction in server memory system 有权
标题翻译：服务器内存系统功耗降低
公开(公告)号：US09311228B2
公开(公告)日：2016-04-12
申请号：US13439457
申请日：2012-04-04
申请人： David M. Daly , Tejas Karkhanis , Valentina Salapura
发明人： David M. Daly , Tejas Karkhanis , Valentina Salapura
IPC分类号： G06F12/00 , G06F12/02 , G06F11/34 , G06F12/06
CPC分类号： G06F12/023 , G06F11/3409 , G06F11/3471 , G06F12/06 , G06F2201/81 , G06F2201/88 , G06F2212/1028 , G06F2212/2532 , G06F2212/502 , Y02D10/13 , Y02D10/34
摘要： A system and method for reducing power consumption of memory chips outside of a host processor device inoperative communication with the memory chips via a memory controller. The memory can operate in modes, such that via the memory controller, the stored data can be localized and moved at various granularities, among ranks established in the chips, to result in fewer operating ranks. Memory chips may then be turned on and off based on host memory access usage levels at each rank in the chip. Host memory access usage levels at each rank in the chip is tracked by performance counters established for association with each rank of a memory chip. Turning on and off of the memory chips is based on a mapping maintained between ranks and address locations corresponding to sub-sections within each rank receiving the host processor access requests.
摘要翻译：一种用于降低主处理器设备外部的存储器芯片的功耗的系统和方法，其经由存储器控制器与存储器芯片无效通信。存储器可以以模式操作，使得经由存储器控制器，存储的数据可以在芯片中建立的等级之间以各种粒度进行本地化和移动，从而导致更少的操作等级。然后可以基于芯片中每个级别的主机存储器访问使用级别来打开和关闭存储器芯片。芯片中每个级别的主机存储器访问使用级别由建立用于与存储器芯片的每个等级相关联的性能计数器跟踪。存储器芯片的导通和关闭是基于维持在对应于接收主机处理器访问请求的每个等级内的子部分的地址位置的地址位置之间的映射。

2. 发明申请

US20130268741A1 POWER REDUCTION IN SERVER MEMORY SYSTEM 有权
标题翻译：服务器内存系统中的电源减少
公开(公告)号：US20130268741A1
公开(公告)日：2013-10-10
申请号：US13439457
申请日：2012-04-04
申请人： David M. Daly , Tejas Karkhanis , Valentina Salapura
发明人： David M. Daly , Tejas Karkhanis , Valentina Salapura
IPC分类号： G06F12/02
CPC分类号： G06F12/023 , G06F11/3409 , G06F11/3471 , G06F12/06 , G06F2201/81 , G06F2201/88 , G06F2212/1028 , G06F2212/2532 , G06F2212/502 , Y02D10/13 , Y02D10/34
摘要： A system and method for reducing power consumption of memory chips outside of a host processor device inoperative communication with the memory chips via a memory controller. The memory can operate in modes, such that via the memory controller, the stored data can be localized and moved at various granularities, among ranks established in the chips, to result in fewer operating ranks. Memory chips may then be turned on and off based on host memory access usage levels at each rank in the chip. Host memory access usage levels at each rank in the chip is tracked by performance counters established for association with each rank of a memory chip. Turning on and off of the memory chips is based on a mapping maintained between ranks and address locations corresponding to sub-sections within each rank receiving the host processor access requests.
摘要翻译：一种用于降低主处理器设备外部的存储器芯片的功耗的系统和方法，其经由存储器控制器与存储器芯片无效通信。存储器可以以模式操作，使得经由存储器控制器，存储的数据可以在芯片中建立的等级之间以各种粒度进行本地化和移动，从而导致更少的操作等级。然后可以基于芯片中每个级别的主机存储器访问使用级别来打开和关闭存储器芯片。芯片中每个级别的主机存储器访问使用级别由建立用于与存储器芯片的每个等级相关联的性能计数器跟踪。存储器芯片的导通和关闭是基于维持在对应于接收主机处理器访问请求的每个等级内的子部分的地址位置的地址位置之间的映射。

3. 发明申请

US20110320765A1 VARIABLE WIDTH VECTOR INSTRUCTION PROCESSOR 审中-公开
标题翻译：可变宽度矢量指示处理器
公开(公告)号：US20110320765A1
公开(公告)日：2011-12-29
申请号：US12825328
申请日：2010-06-28
申请人： Tejas Karkhanis , Jose E. Moreira , Valentina Salapura
发明人： Tejas Karkhanis , Jose E. Moreira , Valentina Salapura
IPC分类号： G06F9/30 , G06F15/76
CPC分类号： G06F9/30112 , G06F9/30014 , G06F9/30036 , G06F9/30109 , G06F9/30123 , G06F9/30141 , G06F9/3851 , G06F15/8076
摘要： A computer processor, method, and computer program product for executing vector processing instructions on a variable width vector register file. An example embodiment is a computer processor that includes an instruction execution unit coupled to a variable width vector register file which contains a number of vector registers, the width of the vector registers is changeable during operation of the computer processor.
摘要翻译：一种用于在可变宽度向量寄存器文件上执行矢量处理指令的计算机处理器，方法和计算机程序产品。示例性实施例是一种计算机处理器，其包括耦合到包含多个向量寄存器的可变宽度向量寄存器文件的指令执行单元，在计算机处理器的操作期间向量寄存器的宽度是可变的。

4. 发明授权

US10078515B2 Tracking operand liveness information in a computer system and performing function based on the liveness information 有权
公开(公告)号：US10078515B2
公开(公告)日：2018-09-18
申请号：US13251441
申请日：2011-10-03
申请人： Michael K Gschwind , Valentina Salapura
发明人： Michael K Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/38 , G06F9/40 , G06F9/46
CPC分类号： G06F9/3834 , G06F9/30076 , G06F9/30105 , G06F9/30127 , G06F9/30185 , G06F9/3832 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/462
摘要： Operand liveness state information is maintained during context switches for current architected operands of executing programs. The current operand state information indicates whether corresponding current operands are enabled or disabled for use by a first program module comprising machine instructions of an instruction set architecture (ISA) for disabling current architected operands. A machine instruction of the first program module accesses a current operand by using the current operand state information to determine whether a previously stored current operand value is accessible by the first program module.

5. 发明授权

US09727336B2 Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers 有权
公开(公告)号：US09727336B2
公开(公告)日：2017-08-08
申请号：US13234785
申请日：2011-09-16
申请人： Michael K. Gschwind , Brett Olsson , Valentina Salapura
发明人： Michael K. Gschwind , Brett Olsson , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/34
CPC分类号： G06F9/3013 , G06F9/30025 , G06F9/30036 , G06F9/30098 , G06F9/30105 , G06F9/30112 , G06F9/3012 , G06F9/3016 , G06F9/30189
摘要： Fine-grained enablement at sub-function granularity. An instruction encapsulates different sub-functions of a function, in which the sub-functions use different sets of registers of a composite register file, and therefore, different sets of functional units. At least one operand of the instruction specifies which set of registers, and therefore, which set of functional units, is to be used in performing the sub-function. The instruction can perform various functions (e.g., move, load, etc.) and a sub-function of the function specifies the type of function (e.g., move-floating point; move-vector; etc.).

6. 发明授权

US09329869B2 Prefix computer instruction for compatibily extending instruction functionality 有权
标题翻译：前缀计算机指令，用于兼容扩展指令功能
公开(公告)号：US09329869B2
公开(公告)日：2016-05-03
申请号：US13251426
申请日：2011-10-03
申请人： Michael K Gschwind , Valentina Salapura
发明人： Michael K Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/38 , G06F9/34
CPC分类号： G06F9/30145 , G06F9/30 , G06F9/30185 , G06F9/34 , G06F9/3826 , G06F9/384
摘要： A prefix instruction is executed and passes operands to a net instruction without storing the operands in an architected resource such that the execution of the next instruction uses the operands provided by the prefix instruction to perform an operation, the operands may be prefix instruction immediate field or a target register of the prefix instruction execution.
摘要翻译：执行前缀指令并将操作数传递到网络指令而不将操作数存储在架构资源中，使得下一条指令的执行使用由前缀指令提供的操作数来执行操作，操作数可以是前缀指令立即字段或前缀指令执行的目标寄存器。

7. 发明授权

US09098408B2 Ticket consolidation for multi-tiered applications 有权
公开(公告)号：US09098408B2
公开(公告)日：2015-08-04
申请号：US13592578
申请日：2012-08-23
申请人： Ruchi Mahindru , Valentina Salapura
发明人： Ruchi Mahindru , Valentina Salapura
IPC分类号： G06F11/00 , G06F11/07 , G06F11/34
CPC分类号： G06F11/07 , G06F11/0709 , G06F11/0784 , G06F11/34 , G06Q10/103 , G06Q10/20
摘要： Consolidating problem tickets for a multi-tiered application may comprise identifying a plurality of correlated virtual machines that are running one or more application components of the multi-tiered application. Problem reports may be identified that are generated by one or more of the plurality of correlated virtual machines and caused by a failure of a same single component of the multi-tiered application. The identified problem reports may be consolidated into a single ticket and placed into a ticket handling system.

8. 发明授权

US08904392B2 Shared performance monitor in a multiprocessor system 有权
标题翻译：多处理器系统中的共享性能监视器
公开(公告)号：US08904392B2
公开(公告)日：2014-12-02
申请号：US13484797
申请日：2012-05-31
申请人： George Chiu , Alan G. Gara , Valentina Salapura
发明人： George Chiu , Alan G. Gara , Valentina Salapura
IPC分类号： G06F9/46 , G06F11/34
CPC分类号： G06F11/348 , G06F11/3409 , G06F2201/86 , G06F2201/88 , Y02D10/34
摘要： A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU is further programmed to monitor event signals issued from non-processor devices.
摘要翻译：用于监视在多处理器系统中发生的事件的性能的性能监视单元（PMU）和方法。多处理器系统包括多个处理器设备单元，用于产生表示处理器设备中事件发生的信号的每个处理器设备，以及用于性能监控的单个共享计数器资源。性能监视器单元由多处理器系统中的所有处理器核共享。 PMU进一步被编程为监视从非处理器设备发出的事件信号。

9. 发明授权

US08904153B2 Vector loads with multiple vector elements from a same cache line in a scattered load operation 有权
标题翻译：在分散加载操作中，来自相同高速缓存行的多个向量元素的向量加载
公开(公告)号：US08904153B2
公开(公告)日：2014-12-02
申请号：US12876321
申请日：2010-09-07
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , Valentina Salapura
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/345 , G06F9/30 , G06F9/38 , G06F15/80
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/3857 , G06F15/8069
摘要： Mechanisms for performing a scattered load operation are provided. With these mechanisms, an extended address is received in a cache memory of a processor. The extended address has a plurality of data element address portions that specify a plurality of data elements to be accessed using the single extended address. Each of the plurality of data element address portions is provided to corresponding data element selector logic units of the cache memory. Each data element selector logic unit in the cache memory selects a corresponding data element from a cache line buffer based on a corresponding data element address portion provided to the data element selector logic unit. Each data element selector logic unit outputs the corresponding data element for use by the processor.
摘要翻译：提供了执行分散加载操作的机构。利用这些机制，扩展地址被接收在处理器的高速缓冲存储器中。扩展地址具有多个数据元素地址部分，其指定使用单个扩展地址来访问的多个数据元素。多个数据元素地址部分中的每一个被提供给高速缓冲存储器的相应数据元素选择器逻辑单元。高速缓冲存储器中的每个数据元素选择器逻辑单元基于提供给数据元素选择器逻辑单元的相应数据元素地址部分从高速缓存行缓冲器中选择相应的数据元素。每个数据元素选择器逻辑单元输出相应的数据元素供处理器使用。

10. 发明授权

US08904118B2 Mechanisms for efficient intra-die/intra-chip collective messaging 有权
标题翻译：有效的片内/片内集体消息传递的机制
公开(公告)号：US08904118B2
公开(公告)日：2014-12-02
申请号：US12986528
申请日：2011-01-07
申请人： Amith R. Mamidala , Valentina Salapura , Robert W. Wisniewski
发明人： Amith R. Mamidala , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F12/10 , G06F12/08 , G06F15/167
CPC分类号： G06F12/0831 , G06F15/167
摘要： Mechanism of efficient intra-die collective processing across the nodelets with separate shared memory coherency domains is provided. An integrated circuit die may include a hardware collective unit implemented on the integrated circuit die. A plurality of cores on the integrated circuit die is grouped into a plurality of shared memory coherence domains. Each of the plurality of shared memory coherence domains is connected to the collective unit for performing collective operations between the plurality of shared memory coherence domains.
摘要翻译：提供了具有单独的共享存储器一致性域的节点之间的有效模内集体处理的机制。集成电路管芯可以包括在集成电路管芯上实现的硬件集合单元。集成电路管芯上的多个核被分组成多个共享存储器相干域。多个共享存储器相干域中的每一个连接到集体单元，用于在多个共享存储器相干域之间执行集合操作。

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