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    • 1. 发明授权
    • Power reduction in server memory system
    • 服务器内存系统功耗降低
    • US09311228B2
    • 2016-04-12
    • US13439457
    • 2012-04-04
    • David M. DalyTejas KarkhanisValentina Salapura
    • David M. DalyTejas KarkhanisValentina Salapura
    • G06F12/00G06F12/02G06F11/34G06F12/06
    • G06F12/023G06F11/3409G06F11/3471G06F12/06G06F2201/81G06F2201/88G06F2212/1028G06F2212/2532G06F2212/502Y02D10/13Y02D10/34
    • A system and method for reducing power consumption of memory chips outside of a host processor device inoperative communication with the memory chips via a memory controller. The memory can operate in modes, such that via the memory controller, the stored data can be localized and moved at various granularities, among ranks established in the chips, to result in fewer operating ranks. Memory chips may then be turned on and off based on host memory access usage levels at each rank in the chip. Host memory access usage levels at each rank in the chip is tracked by performance counters established for association with each rank of a memory chip. Turning on and off of the memory chips is based on a mapping maintained between ranks and address locations corresponding to sub-sections within each rank receiving the host processor access requests.
    • 一种用于降低主处理器设备外部的存储器芯片的功耗的系统和方法,其经由存储器控制器与存储器芯片无效通信。 存储器可以以模式操作,使得经由存储器控制器,存储的数据可以在芯片中建立的等级之间以各种粒度进行本地化和移动,从而导致更少的操作等级。 然后可以基于芯片中每个级别的主机存储器访问使用级别来打开和关闭存储器芯片。 芯片中每个级别的主机存储器访问使用级别由建立用于与存储器芯片的每个等级相关联的性能计数器跟踪。 存储器芯片的导通和关闭是基于维持在对应于接收主机处理器访问请求的每个等级内的子部分的地址位置的地址位置之间的映射。
    • 2. 发明申请
    • POWER REDUCTION IN SERVER MEMORY SYSTEM
    • 服务器内存系统中的电源减少
    • US20130268741A1
    • 2013-10-10
    • US13439457
    • 2012-04-04
    • David M. DalyTejas KarkhanisValentina Salapura
    • David M. DalyTejas KarkhanisValentina Salapura
    • G06F12/02
    • G06F12/023G06F11/3409G06F11/3471G06F12/06G06F2201/81G06F2201/88G06F2212/1028G06F2212/2532G06F2212/502Y02D10/13Y02D10/34
    • A system and method for reducing power consumption of memory chips outside of a host processor device inoperative communication with the memory chips via a memory controller. The memory can operate in modes, such that via the memory controller, the stored data can be localized and moved at various granularities, among ranks established in the chips, to result in fewer operating ranks. Memory chips may then be turned on and off based on host memory access usage levels at each rank in the chip. Host memory access usage levels at each rank in the chip is tracked by performance counters established for association with each rank of a memory chip. Turning on and off of the memory chips is based on a mapping maintained between ranks and address locations corresponding to sub-sections within each rank receiving the host processor access requests.
    • 一种用于降低主处理器设备外部的存储器芯片的功耗的系统和方法,其经由存储器控制器与存储器芯片无效通信。 存储器可以以模式操作,使得经由存储器控制器,存储的数据可以在芯片中建立的等级之间以各种粒度进行本地化和移动,从而导致更少的操作等级。 然后可以基于芯片中每个级别的主机存储器访问使用级别来打开和关闭存储器芯片。 芯片中每个级别的主机存储器访问使用级别由建立用于与存储器芯片的每个等级相关联的性能计数器跟踪。 存储器芯片的导通和关闭是基于维持在对应于接收主机处理器访问请求的每个等级内的子部分的地址位置的地址位置之间的映射。