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1. 发明授权

US09727336B2 Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers 有权
公开(公告)号：US09727336B2
公开(公告)日：2017-08-08
申请号：US13234785
申请日：2011-09-16
申请人： Michael K. Gschwind , Brett Olsson , Valentina Salapura
发明人： Michael K. Gschwind , Brett Olsson , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/34
CPC分类号： G06F9/3013 , G06F9/30025 , G06F9/30036 , G06F9/30098 , G06F9/30105 , G06F9/30112 , G06F9/3012 , G06F9/3016 , G06F9/30189
摘要： Fine-grained enablement at sub-function granularity. An instruction encapsulates different sub-functions of a function, in which the sub-functions use different sets of registers of a composite register file, and therefore, different sets of functional units. At least one operand of the instruction specifies which set of registers, and therefore, which set of functional units, is to be used in performing the sub-function. The instruction can perform various functions (e.g., move, load, etc.) and a sub-function of the function specifies the type of function (e.g., move-floating point; move-vector; etc.).

2. 发明申请

US20130073836A1 FINE-GRAINED INSTRUCTION ENABLEMENT AT SUB-FUNCTION GRANULARITY 有权
公开(公告)号：US20130073836A1
公开(公告)日：2013-03-21
申请号：US13234785
申请日：2011-09-16
申请人： Michael K. Gschwind , Brett Olsson , Valentina Salapura
发明人： Michael K. Gschwind , Brett Olsson , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： G06F9/3013 , G06F9/30025 , G06F9/30036 , G06F9/30098 , G06F9/30105 , G06F9/30112 , G06F9/3012 , G06F9/3016 , G06F9/30189
摘要： Fine-grained enablement at sub-function granularity. An instruction encapsulates different sub-functions of a function, in which the sub-functions use different sets of registers of a composite register file, and therefore, different sets of functional units. At least one operand of the instruction specifies which set of registers, and therefore, which set of functional units, is to be used in performing the sub-function. The instruction can perform various functions (e.g., move, load, etc.) and a sub-function of the function specifies the type of function (e.g., move-floating point; move-vector; etc.).

3. 发明授权

US07877582B2 Multi-addressable register file 失效
标题翻译：多地址寄存器文件
公开(公告)号：US07877582B2
公开(公告)日：2011-01-25
申请号：US12023720
申请日：2008-01-31
申请人： Michael K. Gschwind , Brett Olsson
发明人： Michael K. Gschwind , Brett Olsson
IPC分类号： G06F9/30 , G06F15/76
CPC分类号： G06F9/3013 , G06F9/30036 , G06F9/30098 , G06F9/30109 , G06F9/30112 , G06F9/30145
摘要： A single register file may be addressed using both scalar and SIMD instructions. That is, subsets of registers within a multi-addressable register file according to the illustrative embodiments, are addressable with different instruction forms, e.g., scalar instructions, SIMD instructions, etc., while the entire set of registers may be addressed with yet another form of instructions, referred to herein as Vector-Scalar Extension (VSX) instructions. The operation set that may be performed on the entire set of registers using the VSX instruction form is substantially similar to that of the operation sets of the subsets of registers. Such an arrangement allows legacy instructions to access subsets of registers within the multi-addressable register file while new instructions, i.e. the VSX instructions, may access the entire range of registers within the multi-addressable register file.
摘要翻译：可以使用标量和SIMD指令来寻址单个寄存器文件。也就是说，根据说明性实施例的多可寻址寄存器堆中的寄存器子集可以用不同的指令形式（例如标量指令，SIMD指令等）寻址，而整个寄存器组可以用另一形式的指令，这里称为矢量 - 标量延伸（VSX）指令。可以使用VSX指令形式在整个寄存器组上执行的操作集基本上类似于寄存器子集的操作集。这种布置允许传统指令访问多址寻址寄存器文件内的寄存器子集，而新的指令即VSX指令可以访问多址寻址寄存器堆中的整个寄存器范围。

4. 发明申请

US20090198977A1 Sharing Data in Internal and Memory Representations with Dynamic Data-Driven Conversion 有权
标题翻译：通过动态数据驱动的转换在内部和内存表示中共享数据
公开(公告)号：US20090198977A1
公开(公告)日：2009-08-06
申请号：US12023768
申请日：2008-01-31
申请人： Michael K. Gschwind , Brett Olsson
发明人： Michael K. Gschwind , Brett Olsson
IPC分类号： G06F9/30
CPC分类号： G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3016 , G06F9/30174 , G06F9/30181 , G06F9/3885
摘要： Illustrative embodiments determine the data type of the operand being accessed as well as analyze the data value subrange of the input operand data type. If the operand's data type does not match the required format of the instruction being processed, a determination is made as to whether a subrange of data values of the data type of the input operand is supported natively. If the subrange of data values of the input operand is not supported natively, then a format conversion is performed on the data and the instruction may then operate on the data. Otherwise, the data may be operated on directly by the instruction without a format conversion operation and thus, the conversion is not performed.
摘要翻译：说明性实施例确定被访问的操作数的数据类型以及分析输入操作数数据类型的数据值子范围。如果操作数的数据类型与正在处理的指令的所需格式不匹配，则确定本地是否支持输入操作数的数据类型的数据值的子范围。如果本地不支持输入操作数的数据值的子范围，则对数据进行格式转换，然后该指令可以对数据进行操作。否则，数据可以直接由指令操作，而不进行格式转换操作，因此不进行转换。

5. 发明授权

US09411585B2 Multi-addressable register files and format conversions associated therewith 有权
公开(公告)号：US09411585B2
公开(公告)日：2016-08-09
申请号：US13234520
申请日：2011-09-16
申请人： Michael K. Gschwind , Brett Olsson
发明人： Michael K. Gschwind , Brett Olsson
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30036 , G06F9/30098 , G06F9/30112 , G06F9/3016 , G06F9/30185
摘要： A multi-addressable register file is addressed by a plurality of types of instructions, including scalar, vector and vector-scalar extension instructions. It may be determined that data is to be translated from one format to another format. If so determined, a convert machine instruction is executed that obtains a single precision datum in a first representation in a first format from a first register; converts the single precision datum of the first representation in the first format to a converted single precision datum of a second representation in a second format; and places the converted single precision datum in a second register.

6. 发明申请

US20120297373A1 METHODS FOR GENERATING CODE FOR AN ARCHITECTURE ENCODING AN EXTENDED REGISTER SPECIFICATION 审中-公开
公开(公告)号：US20120297373A1
公开(公告)日：2012-11-22
申请号：US13559274
申请日：2012-07-26
申请人： Michael K. Gschwind , Robert Kevin Montoye , Brett Olsson , John-David Wellman
发明人： Michael K. Gschwind , Robert Kevin Montoye , Brett Olsson , John-David Wellman
IPC分类号： G06F9/45
CPC分类号： G06F8/447
摘要： There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.

7. 发明申请

US20090198966A1 Multi-Addressable Register File 失效
标题翻译：多地址寄存器文件
公开(公告)号：US20090198966A1
公开(公告)日：2009-08-06
申请号：US12023720
申请日：2008-01-31
申请人： Michael K. Gschwind , Brett Olsson
发明人： Michael K. Gschwind , Brett Olsson
IPC分类号： G06F9/30
CPC分类号： G06F9/3013 , G06F9/30036 , G06F9/30098 , G06F9/30109 , G06F9/30112 , G06F9/30145
摘要： A single register file may be addressed using both scalar and SIMD instructions. That is, subsets of registers within a multi-addressable register file according to the illustrative embodiments, are addressable with different instruction forms, e.g., scalar instructions, SIMD instructions, etc., while the entire set of registers may be addressed with yet another form of instructions, referred to herein as Vector-Scalar Extension (VSX) instructions. The operation set that may be performed on the entire set of registers using the VSX instruction form is substantially similar to that of the operation sets of the subsets of registers. Such an arrangement allows legacy instructions to access subsets of registers within the multi-addressable register file while new instructions, i.e. the VSX instructions, may access the entire range of registers within the multi-addressable register file.
摘要翻译：可以使用标量和SIMD指令来寻址单个寄存器文件。也就是说，根据说明性实施例的多可寻址寄存器堆中的寄存器子集可以用不同的指令形式（例如标量指令，SIMD指令等）寻址，而整个寄存器组可以用另一形式的指令，这里称为矢量 - 标量延伸（VSX）指令。可以使用VSX指令形式在整个寄存器组上执行的操作集基本上类似于寄存器子集的操作集。这种布置允许传统指令访问多址寻址寄存器文件内的寄存器子集，而新的指令即VSX指令可以访问多址寻址寄存器堆中的整个寄存器范围。

8. 发明授权

US07849294B2 Sharing data in internal and memory representations with dynamic data-driven conversion 有权
标题翻译：通过动态数据驱动转换在内部和内存表示中共享数据
公开(公告)号：US07849294B2
公开(公告)日：2010-12-07
申请号：US12023768
申请日：2008-01-31
申请人： Michael K. Gschwind , Brett Olsson
发明人： Michael K. Gschwind , Brett Olsson
IPC分类号： G06F9/302 , G06F9/305
CPC分类号： G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3016 , G06F9/30174 , G06F9/30181 , G06F9/3885
摘要： Illustrative embodiments determine the data type of the operand being accessed as well as analyze the data value subrange of the input operand data type. If the operand's data type does not match the required format of the instruction being processed, a determination is made as to whether a subrange of data values of the data type of the input operand is supported natively. If the subrange of data values of the input operand is not supported natively, then a format conversion is performed on the data and the instruction may then operate on the data. Otherwise, the data may be operated on directly by the instruction without a format conversion operation and thus, the conversion is not performed.
摘要翻译：说明性实施例确定被访问的操作数的数据类型以及分析输入操作数数据类型的数据值子范围。如果操作数的数据类型与正在处理的指令的所需格式不匹配，则确定本地是否支持输入操作数的数据类型的数据值的子范围。如果本地不支持输入操作数的数据值的子范围，则对数据进行格式转换，然后该指令可以对数据进行操作。否则，数据可以直接由指令操作，而不进行格式转换操作，因此不进行转换。

9. 发明申请

US20130073838A1 MULTI-ADDRESSABLE REGISTER FILES AND FORMAT CONVERSIONS ASSOCIATED THEREWITH 有权
标题翻译：多址寄存器文件和与之相关的格式转换
公开(公告)号：US20130073838A1
公开(公告)日：2013-03-21
申请号：US13234520
申请日：2011-09-16
申请人： Michael K. Gschwind , Brett Olsson
发明人： Michael K. Gschwind , Brett Olsson
IPC分类号： G06F9/30
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30036 , G06F9/30098 , G06F9/30112 , G06F9/3016 , G06F9/30185
摘要： A multi-addressable register file is addressed by a plurality of types of instructions, including scalar, vector and vector-scalar extension instructions. It may be determined that data is to be translated from one format to another format. If so determined, a convert machine instruction is executed that obtains a single precision datum in a first representation in a first format from a first register; converts the single precision datum of the first representation in the first format to a converted single precision datum of a second representation in a second format; and places the converted single precision datum in a second register.
摘要翻译：多址寻址寄存器文件由多种类型的指令来寻址，包括标量，向量和向量标量扩展指令。可以确定数据将从一种格式转换成另一格式。如果这样确定，则执行转换机器指令，其以第一格式从第一寄存器获得第一表示中的单精度数据; 将第一格式的第一表示的单精度数据转换成第二格式的第二表示的转换单精度数据; 并将转换的单精度数据放在第二个寄存器中。

10. 发明申请

US20110131394A1 APPARATUS AND METHOD FOR USING BRANCH PREDICTION HEURISTICS FOR DETERMINATION OF TRACE FORMATION READINESS 失效
标题翻译：使用分支预测机制确定跟踪形成准备的装置和方法
公开(公告)号：US20110131394A1
公开(公告)日：2011-06-02
申请号：US13016144
申请日：2011-01-28
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F9/40 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。缓存中的跟踪行的形成在系统的初始操作中被延迟，以确保存储的跟踪线的质量。

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