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    • 7. 发明授权
    • Semiconductor circuit and methodology for in-system scan testing
    • 用于系统内扫描测试的半导体电路和方法
    • US09121892B2
    • 2015-09-01
    • US13584630
    • 2012-08-13
    • David LambKendrick Owen Daniel FranzenDavid Hossack
    • David LambKendrick Owen Daniel FranzenDavid Hossack
    • G01R31/28G01R31/27G01R31/3185
    • G01R31/27G01R31/318555
    • A semiconductor circuit comprises a digital circuit portion, which in turn comprises a combinatorial logic block. The semiconductor circuit comprises a scan chain for loading and applying a predefined digital test pattern to inputs of the combinatorial logic block. A bi-directional communication port is adapted for writing incoming data to an address space of the digital circuit portion such as register addresses and/or memory addresses. Scan control hardware comprises a plurality of individually addressable scan control registers which are mapped to the address space of the bi-directional communication port. A method of testing the digital circuit portion through the scan chain involves writing bit values to inputs of the individually addressable scan control registers and reading bit values from at least one output of an individually addressable scan control register.
    • 半导体电路包括数字电路部分,该数字电路部分又包括组合逻辑块。 半导体电路包括扫描链,用于将预定义的数字测试图案加载并应用于组合逻辑块的输入。 双向通信端口适于将输入数据写入数字电路部分的地址空间,例如寄存器地址和/或存储器地址。 扫描控制硬件包括被映射到双向通信端口的地址空间的多个单独可寻址的扫描控制寄存器。 通过扫描链测试数字电路部分的方法涉及将位值写入到可单独寻址的扫描控制寄存器的输入和从单独寻址扫描控制寄存器的至少一个输出读取位值。