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1. 发明授权

US5517665A System for controlling arbitration using the memory request signal types generated by the plurality of datapaths having dual-ported local memory architecture for simultaneous data transmission 失效
标题翻译：用于使用由具有双端口本地存储器架构的多个数据路径生成的存储器请求信号类型来控制仲裁的系统，用于同时数据传输
公开(公告)号：US5517665A
公开(公告)日：1996-05-14
申请号：US230915
申请日：1994-04-21
申请人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Gregory M. Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
发明人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Gregory M. Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
IPC分类号： G06F9/30 , G06F9/38 , G06F15/16 , G06F13/00
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30149 , G06F9/3802 , G06F9/3863 , G06F9/3887
摘要： A system and method for processing data. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor. The system comprises a data bus coupled to the global memory for transferring data to and from the global memory, and a transfer controller for controlling block transfer and scalar data transfers between the local memory and the global memory over the data bus and for arbitrating among competing datapaths of the plurality of datapaths to gram to a selected datapath access to the data bus in accordance with the signal types of the memory request signals generated by datapaths of the plurality of datapaths.
摘要翻译：一种用于处理数据的系统和方法。根据优选实施例，系统包括全局存储器和多个数据路径。每个数据路径包括用于执行指令序列的指令并根据指令提供多个存储器请求信号类型的数据路径处理器，本地存储器，用于在本地存储器和全局存储器之间传送数据的全局端口，以及双重端口包括用于在本地存储器和数据路径处理器之间传送数据的第一和第二本地端口，其中第一和第二本地端口允许在本地存储器和数据路径处理器之间同时传输数据。该系统包括耦合到全局存储器的数据总线，用于将数据传送到全局存储器和从全局存储器传送数据;以及传输控制器，用于通过数据总线控制本地存储器和全局存储器之间的块传输和标量数据传输，并且用于在竞争中进行仲裁根据由多个数据路径的数据路径生成的存储器请求信号的信号类型，将多个数据路径的数据路径克化为对数据总线的选择的数据路径访问。

2. 发明授权

US5548793A System for controlling arbitration using the memory request signal types generated by the plurality of datapaths 失效
标题翻译：用于使用由多个数据路径生成的存储器请求信号类型来控制仲裁的系统
公开(公告)号：US5548793A
公开(公告)日：1996-08-20
申请号：US230899
申请日：1994-04-21
申请人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Gregory M. Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
发明人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Gregory M. Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
IPC分类号： G06F9/30 , G06F9/38 , G06F13/00 , G06F15/16
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30149 , G06F9/3802 , G06F9/3863 , G06F9/3887
摘要： A system and method for arbitrating among memory requests. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, wherein the plurality of memory request signal types comprises instruction memory request signals, scalar memory request signals, first-in and first-out memory request signals, statistical decoder memory request signals, and block transfer memory request signals. Each datapath also comprises local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor. The system comprises a data bus coupled to the global memory for transferring data to and from the global memory, and a transfer controller for controlling block transfer and scalar data transfers between the local memory and the global memory over the data bus and for arbitrating among competing datapaths of the plurality of datapaths to grant to a selected datapath access to the data bus in accordance with the signal types of the memory request signals generated by datapaths of the plurality of datapaths.
摘要翻译：一种用于在存储器请求之间进行仲裁的系统和方法。根据优选实施例，系统包括全局存储器和多个数据路径。每个数据路径包括用于执行指令序列的指令并根据指令提供多个存储器请求信号类型的数据路径处理器，其中多个存储器请求信号类型包括指令存储器请求信号，标量存储器请求信号，输入和先出存储器请求信号，统计解码器存储器请求信号和块传送存储器请求信号。每个数据路径还包括本地存储器，用于在本地存储器和全局存储器之间传送数据的全局端口，以及包括用于在本地存储器和数据路口处理器之间传送数据的第一和第二本地端口的双端口，其中第一和第二本地端口允许在本地存储器和数据路径处理器之间同时传输数据。该系统包括耦合到全局存储器的数据总线，用于将数据传送到全局存储器和从全局存储器传送数据;以及传输控制器，用于通过数据总线控制本地存储器和全局存储器之间的块传输和标量数据传输，并且用于在竞争中进行仲裁根据由多个数据路径的数据路径生成的存储器请求信号的信号类型，多个数据路径的数据路径被授权给对数据总线的选择的数据路径访问。

3. 发明授权

US5530884A System with plurality of datapaths having dual-ported local memory architecture for converting prefetched variable length data to fixed length decoded data 失效
标题翻译：具有多个具有双端口本地存储器架构的数据路径的系统，用于将预取的可变长度数据转换为固定长度解码数据
公开(公告)号：US5530884A
公开(公告)日：1996-06-25
申请号：US230900
申请日：1994-04-21
申请人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Gregory M. Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
发明人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Gregory M. Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
IPC分类号： G06F9/30 , G06F9/38 , G06F3/00 , G06F15/16
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30149 , G06F9/3802 , G06F9/3863 , G06F9/3887
摘要： A method and apparatus for processing data. According to a preferred embodiment, the apparatus comprises a plurality of datapaths, each datapath comprising datapath processor, and a statistical decoder input channel device. The statistical decoder input channel device prefetches variable length encoded data from a variable length encoded data source in response to a request by a program running on a datapath processor of a datapath of the plurality of datapaths. The statistical decoder input channel device comprises a statistical decoder processor and memory for decoding the variable length encoded data to provide fixed length decoded data, and a transmission output channel for transmitting the fixed length decoded data to the datapath.
摘要翻译：一种处理数据的方法和装置。根据优选实施例，该装置包括多个数据路径，每个数据路径包括数据路径处理器和统计解码器输入通道设备。响应于在多个数据路径的数据通路的数据路径处理器上运行的程序的请求，统计解码器输入通道设备从可变长度编码数据源预取可变长度编码数据。统计解码器输入通道装置包括统计解码器处理器和用于解码可变长度编码数据以提供固定长度解码数据的存储器，以及用于将固定长度解码数据发送到数据路径的发送输出通道。

4. 发明授权

US5430854A Simd with selective idling of individual processors based on stored conditional flags, and with consensus among all flags used for conditional branching 失效
标题翻译： Simd根据存储的条件标志对各个处理器进行选择性空闲，并在所有用于条件分支的标志之间保持一致
公开(公告)号：US5430854A
公开(公告)日：1995-07-04
申请号：US144219
申请日：1993-10-27
申请人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Michael Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
发明人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Michael Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
IPC分类号： G06F12/08 , G06F9/30 , G06F9/38 , G06F15/80 , G06T1/20
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30149 , G06F9/3802 , G06F9/3863
摘要： A data processing system having execution units for executing instruction sequences determines at least two conditionals in accordance with the instructions and sets respective flags according to the determined conditionals. These flags are stored and later retrieved sequentially and the execution unit executes selected instructions of the instruction sequence according to the sequentially retrieved mask flags. These masked flags may be stored sequentially in a stack for sequential retrieval at a later time.
摘要翻译：具有用于执行指令序列的执行单元的数据处理系统根据指令确定至少两个条件，并根据确定的条件设置相应的标志。这些标志被依次存储和稍后检索，并且执行单元根据顺序检索的掩码标志来执行指令序列的所选择的指令。这些屏蔽的标志可以顺序地存储在堆栈中，以便在稍后的时间进行顺序检索。

5. 发明授权

US5361370A Single-instruction multiple-data processor having dual-ported local memory architecture for simultaneous data transmission on local memory ports and global port 失效
标题翻译：单指令多数据处理器具有双端口本地存储器架构，用于在本地存储器端口和全局端口上同时进行数据传输
公开(公告)号：US5361370A
公开(公告)日：1994-11-01
申请号：US782332
申请日：1991-10-24
申请人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Michael Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapellil , Vitaly H. Shilman
发明人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Michael Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapellil , Vitaly H. Shilman
IPC分类号： G06F9/30 , G06F9/38 , G06F15/16 , G06F15/66 , G06F15/80
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30149 , G06F9/3802 , G06F9/3863 , G06F9/3887
摘要： A single-instruction multiple-data video signal processor employs a dual-ported local memory architecture in each local memory including a dedicated port for transfers between the local memory and a global memory. A block transfer controller, in combination with the dedicated port, permit each access to the global memory by a datapath processor to be overlapped with its instruction processing, thus usually avoiding stalling of the video signal processor.
摘要翻译：单指令多数据视频信号处理器在每个本地存储器中采用双端口本地存储器架构，包括用于本地存储器和全局存储器之间的传输的专用端口。与专用端口组合的块传送控制器允许数据路径处理器对全局存储器的每个访问与其指令处理重叠，从而通常避免视频信号处理器的停止。

6. 发明授权

US4881194A Stored-program controller for equalizing conditional branch delays 失效
标题翻译：存储程序控制器，用于均衡条件分支延迟
公开(公告)号：US4881194A
公开(公告)日：1989-11-14
申请号：US121820
申请日：1987-11-16
申请人： David L. Sprague , Kevin Harney , Allen H. Simon , Herbert H. Taylor, Jr.
发明人： David L. Sprague , Kevin Harney , Allen H. Simon , Herbert H. Taylor, Jr.
IPC分类号： G06F9/26
CPC分类号： G06F9/267
摘要： A video signal processor includes a stored-program controller which concurrently reads two instruction values from a program memory during each instruction cycle. The next instruction used by the video signal processor is selected from between these two values. If the current instruction indicates a conditional branch operation, the value of one of a plurality of conditions internal to the video signal processor determines which of these two instructions is selected. Otherwise, a value provided by the current instruction itself determines which of the two instructions is selected. This configuration of the stored program controller implements a conditional branch facility in which there is no delay in fetching an instruction for either value of the selected condition.
摘要翻译：视频信号处理器包括存储程序控制器，其在每个指令周期期间同时从程序存储器读取两个指令值。从这两个值之间选择视频信号处理器使用的下一条指令。如果当前指令指示条件分支操作，则视频信号处理器内部的多个条件之一的值确定选择了这两个指令中的哪一个。否则，由当前指令本身提供的值确定选择了两个指令中的哪一个。存储的程序控制器的这种配置实现条件分支设施，其中在为所选择的条件的任一值获取指令时没有延迟。

7. 发明授权

US4823201A Processor for expanding a compressed video signal 失效
标题翻译：用于扩展压缩视频信号的处理器
公开(公告)号：US4823201A
公开(公告)日：1989-04-18
申请号：US121753
申请日：1987-11-16
申请人： Allen H. Simon , David L. Sprague , John M. Keith , Michael F. Patti , Kevin Harney , Lawrence D. Ryan , Nicola J. Fedele , Brian Astle
发明人： Allen H. Simon , David L. Sprague , John M. Keith , Michael F. Patti , Kevin Harney , Lawrence D. Ryan , Nicola J. Fedele , Brian Astle
IPC分类号： G06T9/00 , H04N7/32 , H04N7/13
CPC分类号： H04N19/50
摘要： A parallel-pipeline video signal processing system is disclosed which includes a statistical decoder, an arithmetic and logic unit and a pixel interpolator which operate in parallel under the control of sequencing circuitry to expand a compressed video signal. The video signal may have been developed using a variety of compression techniques including Huffman-type statistical encoding.
摘要翻译：公开了一种并行流水线视频信号处理系统，其包括统计解码器，算术和逻辑单元以及在排序电路的控制下并行操作以扩展压缩视频信号的像素内插器。可以使用包括霍夫曼型统计编码的各种压缩技术来开发视频信号。

8. 发明授权

US5640528A Method and apparatus for translating addresses using mask and replacement value registers 失效
标题翻译：使用掩码和替换值寄存器翻译地址的方法和装置
公开(公告)号：US5640528A
公开(公告)日：1997-06-17
申请号：US469798
申请日：1995-06-06
申请人： Kevin Harney , David L. Sprague
发明人： Kevin Harney , David L. Sprague
IPC分类号： G06F9/30 , G06F9/38 , G06F12/02 , G06F12/10 , G06F12/00
CPC分类号： G06F12/0284 , G06F9/30072 , G06F9/30149 , G06F9/3816 , G06F9/3863 , G06F9/3885
摘要： A method and apparatus for translating a first address in a first address space, such as a processor address space, to a second address in a second address space, such as a system address space, are described. Data alignment signal determinations based on comparisons between destination and source addresses permit automatic replacement of virtual addresses with actual physical addresses to permit direct data transfer between devices. In one embodiment, the apparatus for translating comprises a processor; a page table having a mask register, a comparison value register, and a replacement value register; and a comparator coupled to the comparison value register and to the replacement value register. A programmable mask within the translation mask register is employed to partition a virtual address. A first subaddress comprises a subset of the bits of the first address and a second subaddress comprises remaining bits of the first address. The first subaddress is masked with a programmable mask value in the translation mask register and is compared by the comparator with successive comparison values in the comparison value register until a match comparison value is found. A programmable replacement value in the replacement value register corresponding to the match comparison value is concatenated with the second subaddress. The programmable replacement values, which correspond to programable map windows, permit the programmable mapping of virtual addresses into different predetermined regions of system virtual address space.
摘要翻译：描述了用于将诸如处理器地址空间的第一地址空间中的第一地址转换到诸如系统地址空间的第二地址空间中的第二地址的方法和装置。基于目的地址和源地址之间的比较的数据对准信号确定允许使用实际物理地址自动替换虚拟地址，以允许设备之间的直接数据传输。在一个实施例中，用于翻译的装置包括处理器; 具有掩模寄存器，比较值寄存器和替换值寄存器的页表; 以及耦合到比较值寄存器和替换值寄存器的比较器。使用翻译掩码寄存器内的可编程掩码来分割虚拟地址。第一子地址包括第一地址的比特的子集，第二子地址包括第一地址的剩余比特。第一个子地址在转换掩码寄存器中用可编程掩码值屏蔽，并通过比较器与比较值寄存器中的连续比较值进行比较，直到找到匹配比较值。对应于匹配比较值的替换值寄存器中的可编程替换值与第二子地址相连。对应于可编程地图窗口的可编程替换值允许将虚拟地址可编程映射到系统虚拟地址空间的不同预定区域。

9. 发明授权

US4816913A Pixel interpolation circuitry as for a video signal processor 失效
标题翻译：像素插值电路，用于视频信号处理器
公开(公告)号：US4816913A
公开(公告)日：1989-03-28
申请号：US121021
申请日：1987-11-16
申请人： Kevin Harney , John M. Keith , David L. Sprague , Brian Astle
发明人： Kevin Harney , John M. Keith , David L. Sprague , Brian Astle
IPC分类号： H04N7/26 , G06F17/17 , H04N7/46 , H04N7/13
CPC分类号： H04N19/59 , G06F17/17
摘要： A processor for expanding a compressed video signal includes a pixel interpolator which interpolates between input pixel values in two dimensions. This interpolator calculates and stores intermediate pixel values which are interpolated in the vertical direction. A pair of these intermediate pixel values are then fed back into the interpolator which performs a horizontal interpolation to produce pixel values that are interpolated in both the horizontal and vertical dimensions. In steady state operation, the horizontal and vertical interpolation operations are alternated to produce a stream of two-dimensionally interpolated values.
摘要翻译：用于扩展压缩视频信号的处理器包括在二维输入像素值之间插值的像素内插器。该内插器计算并存储在垂直方向上插值的中间像素值。然后将一对这些中间像素值反馈到内插器中，该内插器执行水平内插以产生在水平和垂直维度上内插的像素值。在稳态操作中，水平和垂直内插操作被交替以产生二维内插值流。

10. 发明授权

US5187793A Processor with hierarchal memory and using meta-instructions for software control of loading, unloading and execution of machine instructions stored in the cache 失效
标题翻译：具有分层存储器的处理器，并使用元指令对软件进行加载，卸载和执行存储在缓存中的机器指令的软件控制
公开(公告)号：US5187793A
公开(公告)日：1993-02-16
申请号：US294888
申请日：1989-01-09
申请人： John M. Keith , Allen H. Simon , David L. Sprague , Douglas F. Dixon , Judith A. Goldstein
发明人： John M. Keith , Allen H. Simon , David L. Sprague , Douglas F. Dixon , Judith A. Goldstein
IPC分类号： G06F9/318 , G06F9/38 , G06F12/08
CPC分类号： G06F9/3802 , G06F12/0802 , G06F9/3017
摘要： An instruction caching system comprises meta-instructions which are contained within the program being executed. A meta-machine, which is a small segment of software, executes the meta-instructions and passes control to the processor itself at appropriate times to execute blocks of instructions from the instruction cache.
摘要翻译：指令高速缓存系统包括包含在正在执行的程序内的元指令。作为小部分软件的元机器在适当的时间执行元指令并将控制传递给处理器本身，以执行来自指令高速缓存的指令块。

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