专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5579527A Apparatus for alternately activating a multiplier and a match unit 失效
标题翻译：用于交替激活乘法器和匹配单元的装置
公开(公告)号：US5579527A
公开(公告)日：1996-11-26
申请号：US405434
申请日：1995-03-14
申请人： Danny Chin , Joseph E. Peters, Jr. , Herbert H. Taylor, Jr.
发明人： Danny Chin , Joseph E. Peters, Jr. , Herbert H. Taylor, Jr.
IPC分类号： G06F15/80 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3842 , G06F15/8023 , G06F9/30036 , G06F9/345 , G06F9/3455 , G06F9/355 , G06F9/3552 , G06F9/3879 , G06F9/3887
摘要： A processor for use in a parallel computing system. The processor contains: a memory for storing operand values; an arithmetic logic unit (ALU) for performing arithmetic logic operations on operand values; a multiplier, separate from the ALU and coupled to the memory, for generating arithmetic products of a first operand value and a second operand values; and a match unit, separate from the ALU and coupled to the memory, for detecting matches between a predetermined bit pattern and a sequence of bits retrieved from the memory. The match unit also generates a count value indicating a number of detected matches between the predetermined bit pattern and subsequences of bits within the sequence of bits. The first operand value contains the bit pattern and the second operand contains the sequence of bits.
摘要翻译：一种用于并行计算系统的处理器。处理器包含：用于存储操作数值的存储器; 用于对操作数值执行算术逻辑运算的算术逻辑单元（ALU）; 乘法器，与ALU分离并耦合到存储器，用于产生第一操作数值和第二操作数值的算术乘积; 以及与ALU分离并耦合到存储器的匹配单元，用于检测预定位模式与从存储器检索的位序列之间的匹配。匹配单元还产生指示在比特序列内的预定比特模式和比特的子序列之间的检测到的匹配数的计数值。第一个操作数值包含位模式，第二个操作数包含位序列。

2. 发明授权

US4881194A Stored-program controller for equalizing conditional branch delays 失效
标题翻译：存储程序控制器，用于均衡条件分支延迟
公开(公告)号：US4881194A
公开(公告)日：1989-11-14
申请号：US121820
申请日：1987-11-16
申请人： David L. Sprague , Kevin Harney , Allen H. Simon , Herbert H. Taylor, Jr.
发明人： David L. Sprague , Kevin Harney , Allen H. Simon , Herbert H. Taylor, Jr.
IPC分类号： G06F9/26
CPC分类号： G06F9/267
摘要： A video signal processor includes a stored-program controller which concurrently reads two instruction values from a program memory during each instruction cycle. The next instruction used by the video signal processor is selected from between these two values. If the current instruction indicates a conditional branch operation, the value of one of a plurality of conditions internal to the video signal processor determines which of these two instructions is selected. Otherwise, a value provided by the current instruction itself determines which of the two instructions is selected. This configuration of the stored program controller implements a conditional branch facility in which there is no delay in fetching an instruction for either value of the selected condition.
摘要翻译：视频信号处理器包括存储程序控制器，其在每个指令周期期间同时从程序存储器读取两个指令值。从这两个值之间选择视频信号处理器使用的下一条指令。如果当前指令指示条件分支操作，则视频信号处理器内部的多个条件之一的值确定选择了这两个指令中的哪一个。否则，由当前指令本身提供的值确定选择了两个指令中的哪一个。存储的程序控制器的这种配置实现条件分支设施，其中在为所选择的条件的任一值获取指令时没有延迟。

3. 发明授权

US5581778A Advanced massively parallel computer using a field of the instruction to selectively enable the profiling counter to increase its value in response to the system clock 失效
标题翻译：先进的大规模并行计算机使用该指令的领域来选择性地使分析计数器响应于系统时钟增加其值
公开(公告)号：US5581778A
公开(公告)日：1996-12-03
申请号：US416932
申请日：1995-04-04
申请人： Danny Chin , Joseph E. Peters, Jr. , Herbert H. Taylor, Jr.
发明人： Danny Chin , Joseph E. Peters, Jr. , Herbert H. Taylor, Jr.
IPC分类号： G06F15/80 , G06F13/00
CPC分类号： G06F15/8015 , G06F15/8023 , G06F9/3885 , G06F9/3887
摘要： A parallel computing system comprising N blocks of processors, where N is an integer greater than 1. Each block of the N blocks of processors contains M processors, where M is an integer greater than 1. Each processor includes an arithmetic logic unit (ALU), a local memory and an input/output (I/O) interface. The computing system also contains a control means, connected to each of the M processors, for providing identical instructions to each of the M processors, and a host means, coupled to each of the control means within the N blocks of processors. The host means selectively organizes the control means of each of the N blocks of M processors into at least two groups of P blocks of M processors, P being an integer less than or equal to N. In operation, the host means causes the control means within each group of P blocks of M processors to provide each group of P blocks of M processors respectively different identical processor instructions. To facilitate communications amongst the processors, the parallel computing system includes an interprocessor communications channel that selectively interconnects the processors.
摘要翻译：包括N个处理器块的并行计算系统，其中N是大于1的整数。N个处理器块的每个块包含M个处理器，其中M是大于1的整数。每个处理器包括算术逻辑单元（ALU），本地存储器和输入/输出（I / O）接口。所述计算系统还包含连接到所述M个处理器中的每一个的控制装置，用于向所述M个处理器中的每一个提供相同的指令;以及主机装置，其耦合到所述N个处理器块内的每个所述控制装置。主机装置选择性地将M个处理器的N个块中的每一个的控制装置组织成M个处理器的至少两组P块，P是小于或等于N的整数。在操作中，主机装置使控制装置在M个处理器的每个P块组内，分别提供不同的相同处理器指令的M个处理器的每组P块。为了促进处理器之间的通信，并行计算系统包括选择性地互连处理器的处理器间通信信道。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式