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1. 发明授权

US6078981A Transaction stall technique to prevent livelock in multiple-processor systems 失效
标题翻译：事务处理技术，以防止多处理器系统中的活动锁定
公开(公告)号：US6078981A
公开(公告)日：2000-06-20
申请号：US999244
申请日：1997-12-29
申请人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Paul Breuder , Matthew A. Fisch
发明人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Paul Breuder , Matthew A. Fisch
IPC分类号： G06F13/36 , G06F13/14
CPC分类号： G06F13/36
摘要： A livelock preventative measure is provided for agents in a multi-processor computing system. Livelock may occur when multiple agents each trade ownership of data in an attempt to modify it. When livelock occurs, a first agent posts a bus transaction for a data and, if a second agent posts a bus transaction for the same data, the first agent may stall the bus transaction of the second agent until the first agent has completed its operation on the data.
摘要翻译：为多处理器计算系统中的代理提供了活动预防措施。当多个代理人各自交易数据的所有权以尝试修改数据时，可能会发生活动锁。当发生活动锁定时，第一代理人为数据发布总线事务，并且如果第二代理人为同一数据发布总线事务，则第一代理可以停止第二代理的总线事务，直到第一代理完成其操作数据。

2. 发明授权

US06216208B1 Prefetch queue responsive to read request sequences 失效
标题翻译：预读队列响应读请求序列
公开(公告)号：US06216208B1
公开(公告)日：2001-04-10
申请号：US08999241
申请日：1997-12-29
申请人： Robert Greiner , David L. Hill , Chinna Prudvi , Derek T. Bachand , Matthew A. Fisch
发明人： Robert Greiner , David L. Hill , Chinna Prudvi , Derek T. Bachand , Matthew A. Fisch
IPC分类号： G05F1208
CPC分类号： G06F9/383 , G06F12/0862 , G06F2212/6026
摘要： A prefetching control system provided for a processor. The prefetching queue may include an arbiter, a cache queue and a prefetch queue. The arbiter issues requests including read requests. Responsive to a read request, the cache queue issues a control signal. The prefetch queue receives the control signal and an address associated with the read request. When the received address is a member of a pattern of read requests from sequential memory locations, the prefetch queue issues a prefetch request to the arbiter.
摘要翻译：为处理器提供的预取控制系统。预取队列可以包括仲裁器，高速缓存队列和预取队列。仲裁器发出请求，包括读取请求。响应于读取请求，缓存队列发出控制信号。预取队列接收控制信号和与读取请求相关联的地址。当接收到的地址是来自顺序存储器位置的读取请求的模式的成员时，预取队列向仲裁器发出预取请求。

3. 发明授权

US06209068B1 Read line buffer and signaling protocol for processor 失效
标题翻译：用于处理器的读行缓冲器和信令协议
公开(公告)号：US06209068B1
公开(公告)日：2001-03-27
申请号：US08999242
申请日：1997-12-29
申请人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Matthew A. Fisch
发明人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Matthew A. Fisch
IPC分类号： G06F1216
CPC分类号： G06F12/0831
摘要： A data control method in a microprocessor is disclosed. According to the method, a request is generated on an external bus for data to be read to the processor. The requested data is read from the external bus to an intermediate memory in the processor and, thereafter, read from the intermediate memory to a destination. When the intermediate memory is full, the read of data from the external bus is stalled until the intermediate memory is no longer full. Typically, stalling is accomplished by generating a stall signal on the external bus, which may be generated during a cache coherency phase of the transaction to which the requested data relates.
摘要翻译：公开了一种微处理器中的数据控制方法。根据该方法，在外部总线上生成要向处理器读取的数据的请求。所请求的数据从外部总线读取到处理器中的中间存储器，然后从中间存储器读取到目的地。当中间存储器满时，来自外部总线的数据读取停止，直至中间存储器不再满。通常，停止是通过在外部总线上生成停止信号来实现的，该停止信号可以在所请求的数据所关联的事务的高速缓存一致性阶段期间产生。

4. 发明授权

US06668309B2 Snoop blocking for cache coherency 有权
公开(公告)号：US06668309B2
公开(公告)日：2003-12-23
申请号：US10352946
申请日：2003-01-29
申请人： Derek T. Bachand , Paul Breuder , Matthew A. Fisch
发明人： Derek T. Bachand , Paul Breuder , Matthew A. Fisch
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If the match indicator signal indicates a match, a snoop probe for the bus transaction is blocked.

5. 发明授权

US06578116B2 Snoop blocking for cache coherency 有权
公开(公告)号：US06578116B2
公开(公告)日：2003-06-10
申请号：US10215599
申请日：2002-08-09
申请人： Derek T. Bachand , Paul Breuder , Matthew A. Fisch
发明人： Derek T. Bachand , Paul Breuder , Matthew A. Fisch
IPC分类号： G06G1200
CPC分类号： G06F12/0831
摘要： In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If the match indicator signal indicates a match, a snoop probe for the bus transaction is blocked.

6. 发明授权

US06460119B1 Snoop blocking for cache coherency 有权
公开(公告)号：US06460119B1
公开(公告)日：2002-10-01
申请号：US09210641
申请日：1998-12-14
申请人： Derek T. Bachand , Paul Breuder , Matthew A. Fisch
发明人： Derek T. Bachand , Paul Breuder , Matthew A. Fisch
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If the match indicator signal indicates a match, a snoop probe for the bus transaction is blocked.

7. 发明授权

US5572702A Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency 失效
公开(公告)号：US5572702A
公开(公告)日：1996-11-05
申请号：US202790
申请日：1994-02-28
申请人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14
CPC分类号： G06F12/0831 , G06F12/0833 , G06F13/1668
摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.

8. 发明授权

US5909699A Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency 失效
标题翻译：用于支持对存储器进行读取，写入和无效操作的方法和装置，其保持缓存一致性
公开(公告)号：US5909699A
公开(公告)日：1999-06-01
申请号：US672422
申请日：1996-06-28
申请人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14
CPC分类号： G06F12/0831 , G06F12/0833 , G06F13/1668
摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.
摘要翻译：总线上代理发出的内存请求在保持缓存一致性的同时得到满足。请求代理可以通过将请求放在总线上向另一代理或存储器单元发出请求。总线上的每个代理都会窥探总线，以确定是否可以通过访问其缓存来满足发出的请求。可以使用其缓存来满足请求的代理，即窥探代理，向请求代理发出指示这样的信号。侦听代理将与请求相对应的高速缓存行放置在由请求代理检索到的总线上。在读取请求的情况下，存储器单元还从总线检索高速缓存线数据，并将高速缓存行存储在主存储器中。在写请求的情况下，请求代理随着请求传送总线上的写数据。该写入数据由临时存储数据的存储单元和监听代理二者检索。随后，窥探代理通过总线传输整个高速缓存行。存储器单元检索该高速缓存线，将其与先前存储的写数据合并，并将合并的高速缓存行写入存储器。

9. 发明授权

US5535345A Method and apparatus for sequencing misaligned external bus transactions in which the order of completion of corresponding split transaction requests is guaranteed 失效
标题翻译：用于对未对准的外部总线事务进行排序的方法和装置，其中保证相应的分批交易请求的完成顺序
公开(公告)号：US5535345A
公开(公告)日：1996-07-09
申请号：US241964
申请日：1994-05-12
申请人： Matthew A. Fisch , James M. Brayton , Ajay Malhotra
发明人： Matthew A. Fisch , James M. Brayton , Ajay Malhotra
IPC分类号： G06F15/17 , H01J13/00
CPC分类号： G06F15/17
摘要： In accordance with the preferred embodiment of the present invention, a bus interface unit of a microprocessor is provided with a Micro Request Sequencer (EBMRS) disposed between a bus scheduling queue (EBBQ) and external bus control logic (EBCTL). Under normal bus request traffic, the EBMRS is effectively transparent and allows normal communication between the EBCTL and the EBBQ. However, for misaligned bus transactions, which comprise memory accesses that cross a bus width boundary, the EBMRS intercepts such transactions for special sequencing, while blocking any further requests from the EBBQ. The EBMRS separates each misaligned bus transaction request into at least first and second split transaction requests, with each split request forming a memory access that does not cross a data bus width boundary of the external bus. It then issues the first split request to the EBCTL for processing on the external bus. External bus agents involved with processing of the split requests then return first response information regarding the completion of the first split request. If the first response information indicates that the first split request will complete without being deferred or retried, the EBMRS issues the second split request to the EBCTL for processing on the external bus. Upon the receipt of second response information for the second split request indicating that the second split request is guaranteed to complete without being deferred or retried, the EBMRS then issues any further transaction requests received from the EBBQ without jeopardizing the order dependency of the split requests or subsequent bus transaction requests buffered in the EBBQ.
摘要翻译：根据本发明的优选实施例，微处理器的总线接口单元设置有布置在总线调度队列（EBBQ）和外部总线控制逻辑（EBCTL）之间的微请求排序器（EBMRS）。在正常总线请求流量下，EBMRS有效透明，允许EBCTL和EBBQ之间进行正常通信。然而，对于包含跨越总线宽度边界的存储器访问的未对齐总线事务，EBMRS拦截这种事务以进行特殊排序，同时阻止来自EBBQ的任何进一步的请求。 EBMRS将每个不对齐的总线事务请求分成至少第一和第二分组事务请求，每个分离请求形成不跨越外部总线的数据总线宽度边界的存储器访问。然后，它向EBCTL发出第一个分离请求，以在外部总线上进行处理。涉及处理分离请求的外部总线代理然后返回关于完成第一个分离请求的第一响应信息。如果第一个响应信息指示第一个分离请求将在不延迟或重试的情况下完成，则EBMRS向EBCTL发出第二个分离请求以在外部总线上进行处理。在接收到指示第二分裂请求被保证完成而不被延迟或重试的第二分组请求的第二响应信息时，EBMRS然后发出从EBBQ接收的任何进一步的事务请求，而不会危害分离请求的顺序依赖性，在EBBQ中缓存的后续总线事务请求。

10. 发明授权

US5901297A Initialization mechanism for symmetric arbitration agents 失效
标题翻译：对称仲裁机构的初始化机制
公开(公告)号：US5901297A
公开(公告)日：1999-05-04
申请号：US974750
申请日：1997-11-19
申请人： Matthew A. Fisch , Michael W. Rhodehamel , Nitin Sarangdhar
发明人： Matthew A. Fisch , Michael W. Rhodehamel , Nitin Sarangdhar
IPC分类号： G06F15/00 , G06F9/02 , G06F13/36 , G06F13/362 , G06F13/374 , G06F15/16
CPC分类号： G06F13/362 , G06F13/374
摘要： An initialization mechanism for symmetric arbitration agents ensures that multiple agents on a bus are each initialized with a different arbitration counter value. The arbitration counter of each bus agent is used to keep track of which agent was the last or current owner of the bus and which agent will be the next owner of the bus. All bus agents agree on which agent will be the priority agent at system reset and thus be allowed first ownership of the bus. Each agent's arbitration counter is initialized according to each agent's own agent identification. The arbitration pins of the bus agents are interconnected such that each agent determines for itself a unique agent identification based on which pin of its arbitration pins is active at system reset and the maximum number of bus agents allowed on the bus. After determining its agent identification, each bus agent initializes its arbitration counter such that every agent agrees which agent is the priority agent. Each agent performs this initialization based on its agent identification, the identity of the priority agent, and the maximum number of agents allowed on the bus.
摘要翻译：对称仲裁代理的初始化机制确保总线上的多个代理各自以不同的仲裁计数器值进行初始化。每个总线代理人的仲裁柜台用于跟踪哪个代理人是公交车的最后或当前所有者，哪个代理人将是公共汽车的下一个所有者。所有总线代理商都同意在系统复位时哪个代理将是优先代理，从而允许首先拥有总线。每个代理的仲裁计数器根据每个代理人的代理身份进行初始化。总线代理的仲裁引脚相互连接，使得每个代理人自身可以根据其仲裁引脚的哪个引脚在系统复位时被激活，并在总线上允许的总线代理的最大数量来确定唯一的代理识别。在确定其代理身份后，每个总线代理人初始化其仲裁柜台，以便每个代理商同意哪个代理机构是优先代理。每个代理根据其代理标识，优先级代理的身份以及总线上允许的代理的最大数量来执行此初始化。

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