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1. 发明授权

US06668309B2 Snoop blocking for cache coherency 有权
公开(公告)号：US06668309B2
公开(公告)日：2003-12-23
申请号：US10352946
申请日：2003-01-29
申请人： Derek T. Bachand , Paul Breuder , Matthew A. Fisch
发明人： Derek T. Bachand , Paul Breuder , Matthew A. Fisch
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If the match indicator signal indicates a match, a snoop probe for the bus transaction is blocked.

2. 发明授权

US06578116B2 Snoop blocking for cache coherency 有权
公开(公告)号：US06578116B2
公开(公告)日：2003-06-10
申请号：US10215599
申请日：2002-08-09
申请人： Derek T. Bachand , Paul Breuder , Matthew A. Fisch
发明人： Derek T. Bachand , Paul Breuder , Matthew A. Fisch
IPC分类号： G06G1200
CPC分类号： G06F12/0831
摘要： In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If the match indicator signal indicates a match, a snoop probe for the bus transaction is blocked.

3. 发明授权

US06460119B1 Snoop blocking for cache coherency 有权
公开(公告)号：US06460119B1
公开(公告)日：2002-10-01
申请号：US09210641
申请日：1998-12-14
申请人： Derek T. Bachand , Paul Breuder , Matthew A. Fisch
发明人： Derek T. Bachand , Paul Breuder , Matthew A. Fisch
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If the match indicator signal indicates a match, a snoop probe for the bus transaction is blocked.

4. 发明授权

US6078981A Transaction stall technique to prevent livelock in multiple-processor systems 失效
标题翻译：事务处理技术，以防止多处理器系统中的活动锁定
公开(公告)号：US6078981A
公开(公告)日：2000-06-20
申请号：US999244
申请日：1997-12-29
申请人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Paul Breuder , Matthew A. Fisch
发明人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Paul Breuder , Matthew A. Fisch
IPC分类号： G06F13/36 , G06F13/14
CPC分类号： G06F13/36
摘要： A livelock preventative measure is provided for agents in a multi-processor computing system. Livelock may occur when multiple agents each trade ownership of data in an attempt to modify it. When livelock occurs, a first agent posts a bus transaction for a data and, if a second agent posts a bus transaction for the same data, the first agent may stall the bus transaction of the second agent until the first agent has completed its operation on the data.
摘要翻译：为多处理器计算系统中的代理提供了活动预防措施。当多个代理人各自交易数据的所有权以尝试修改数据时，可能会发生活动锁。当发生活动锁定时，第一代理人为数据发布总线事务，并且如果第二代理人为同一数据发布总线事务，则第一代理可以停止第二代理的总线事务，直到第一代理完成其操作数据。

5. 发明授权

US06269465B1 Error correction system in a processing agent having minimal delay 有权
标题翻译：具有最小延迟的处理代理中的纠错系统
公开(公告)号：US06269465B1
公开(公告)日：2001-07-31
申请号：US09197582
申请日：1998-11-23
申请人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Paul Breuder
发明人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Paul Breuder
IPC分类号： H03M1300
CPC分类号： H03M13/03
摘要： An error correction system in an agent provides an error correction in a circuit path extending from an internal cache to an output of the agent. When data errors are detected for data to be processed internally within the agent, the error correction system passes the corrupted data through the error correction circuit, and out of the agent and back into the agent. The error correction changes internal data requests into an external transaction when data errors are detected.
摘要翻译：代理中的纠错系统在从内部高速缓存延伸到代理的输出的电路中提供纠错。当检测到在代理内部要处理的数据的数据错误时，纠错系统将损坏的数据通过纠错电路，并从代理程序中传回代理。当检测到数据错误时，错误修正将内部数据请求更改为外部事务。

6. 发明授权

US06412091B2 Error correction system in a processing agent having minimal delay 有权
标题翻译：具有最小延迟的处理代理中的纠错系统
公开(公告)号：US06412091B2
公开(公告)日：2002-06-25
申请号：US09848261
申请日：2001-05-04
申请人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Paul Breuder
发明人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Paul Breuder
IPC分类号： H03M1300
CPC分类号： H03M13/03
摘要： An error correction system in an agent provides an error correction in a circuit path extending from an internal cache to an output of the agent. When data errors are detected for data to be processed internally within the agent, the error correction system passes the corrupted data through the error correction circuit, and out of the agent and back into the agent. The error correction changes internal data requests into an external transaction when data errors are detected.
摘要翻译：代理中的纠错系统在从内部高速缓存延伸到代理的输出的电路中提供纠错。当检测到在代理内部要处理的数据的数据错误时，纠错系统将损坏的数据通过纠错电路，并从代理程序中传回代理。当检测到数据错误时，错误修正将内部数据请求更改为外部事务。

7. 发明授权

US06378048B1 “SLIME” cache coherency system for agents with multi-layer caches 有权
标题翻译：具有多层缓存的代理的“SLIME”高速缓存一致性系统
公开(公告)号：US06378048B1
公开(公告)日：2002-04-23
申请号：US09190126
申请日：1998-11-12
申请人： Chinna Prudvi , Paul Breuder , Quinn W. Merrill , Derek Bachand , Harish kumar Kumar , Brent E. Lince
发明人： Chinna Prudvi , Paul Breuder , Quinn W. Merrill , Derek Bachand , Harish kumar Kumar , Brent E. Lince
IPC分类号： G06F1300
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A cache coherency method, a data eviction method, and a multi-level cache system are disclosed. A copy of data may take one of five states including a shared state, a lazy state, an invalid state, a modified state, and an exclusive state. Based upon the names of these states, the disclosed methods and systems may be labeled “SLIME.” The method of cache coherency may include storing a copy of data in a cache and storing state information identifying the copy as being stored in one of the five above-mentioned states. In response to a snoop request related to the data, marking a status field indicative of the state of the data to represent that the data is shared without regard to the data's dirty status. The data eviction method includes storing data in a cache, storing a status field in association with the data, the status field having a first sub-field to indicate whether the data is dirty and a second sub-field to indicate whether the data is shared, when the data is to be evicted from the cache, testing the first sub-field field to determine whether the data is dirty and, if so, writing the data to another cache before evicting the data from the cache. The multi-layer cache system includes first and second caches provided in a layered arrangement with the second cache being in a higher layer than the first cache, each cache including cache entries adapted to store data and status fields associated with the data, the status field representing the state of the data, eviction logic in the first cache adapted to test the status field of a cache entry, and control logic adapted to output the contents of the cache entry to a cache entry in the second cache when the status field indicates that data in the cache entry is dirty.
摘要翻译：公开了高速缓存一致性方法，数据驱逐方法和多级缓存系统。数据副本可以采用共享状态，懒惰状态，无效状态，修改状态和独占状态的五种状态之一。根据这些州的名称，所公开的方法和系统可以标记为“SLIME”。高速缓存一致性的方法可以包括将数据副本存储在高速缓冲存储器中，并将识别复制件的状态信息存储为以上述五个状态之一存储。响应于与数据相关的窥探请求，标记指示数据状态的状态字段以表示数据被共享而不考虑数据的脏状态。数据驱逐方法包括将数据存储在高速缓存中，与数据相关联地存储状态字段，状态字段具有第一子字段以指示数据是否脏，还有第二子字段指示数据是否被共享当数据要从缓存中逐出时，测试第一个子字段以确定数据是否是脏的，如果是这样，则在从缓存中取出数据之前将数据写入另一个高速缓存。多层缓存系统包括以分层布置提供的第一和第二高速缓存，其中第二高速缓存处于比第一高速缓存更高的层中，每个高速缓存包括适于存储与数据相关联的数据和状态字段的高速缓存条目，状态字段表示数据的状态，适于测试高速缓存条目的状态字段的第一高速缓存中的逐出逻辑以及适于在高速缓存条目的内容输出到第二高速缓存中的高速缓存条目的控制逻辑，当状态字段指示缓存条目中的数据很脏。

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