专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08546230B2 Bipolar transistor with a collector having a protected outer edge portion for reduced based-collector junction capacitance and a method of forming the transistor 有权
标题翻译：具有集电器的双极晶体管具有受保护的外边缘部分，用于降低基极集电极结电容，以及形成晶体管的方法
公开(公告)号：US08546230B2
公开(公告)日：2013-10-01
申请号：US13296496
申请日：2011-11-15
申请人： James W. Adkisson , David L. Harame , Robert K. Leidy , Qizhi Liu
发明人： James W. Adkisson , David L. Harame , Robert K. Leidy , Qizhi Liu
IPC分类号： H01L21/331 , H01L29/66
CPC分类号： H01L29/732 , H01L29/7371
摘要： Disclosed are embodiments of a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a collector region having a protected upper edge portion for reduced base-collector junction capacitance Cbc. In the embodiments, a collector region is positioned laterally adjacent to a trench isolation region within a substrate. Mask layer(s) cover the trench isolation region and further extend laterally onto the edge portion of the collector region. A first section of an intrinsic base layer is positioned above a center portion of the collector region and a second section of the intrinsic base layer is positioned above the mask layer(s). During processing these mask layer(s) prevent divot formation in the upper corner of the trench isolation region at the isolation region-collector region interface and further limit dopant diffusion from a subsequently formed raised extrinsic base layer into the collector region.
摘要翻译：公开了晶体管（例如双极结型晶体管（BJT）或异质结双极晶体管（HBT））的实施例以及形成具有集电极区域的晶体管的方法，该集电极区域具有用于还原的基极 - 集电极结电容Cbc的受保护的上边缘部分。在实施例中，集电极区域位于衬底内侧向与沟槽隔离区域相邻的位置。掩模层覆盖沟槽隔离区域并且进一步横向延伸到收集器区域的边缘部分上。本征基极层的第一部分位于集电极区域的中心部分的上方，并且本征基极层的第二部分位于掩模层之上。在处理期间，这些掩模层防止在隔离区域 - 集电极区界面处的沟槽隔离区的上角部形成裂缝，并且进一步限制从随后形成的凸起的外在基极层到集电极区域的掺杂剂扩散。

2. 发明授权

US08610174B2 Bipolar transistor with a raised collector pedestal for reduced capacitance 有权
标题翻译：双极晶体管带有集电极基座，用于降低电容
公开(公告)号：US08610174B2
公开(公告)日：2013-12-17
申请号：US13307412
申请日：2011-11-30
申请人： James W. Adkisson , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
发明人： James W. Adkisson , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
IPC分类号： H01L31/109
CPC分类号： H01L29/66234 , H01L29/0826 , H01L29/66287 , H01L29/732 , H01L29/7371
摘要： Disclosed is a transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently, base-collector junction capacitance is reduced and, consequently, the maximum oscillation frequency is increased.
摘要翻译：公开了具有降低的集电极基座的晶体管，用于减小基极 - 集电极结电容。凸起的收集器基座位于基板的顶表面上，垂直延伸穿过绝缘层（未掺杂或低掺杂）在衬底内的子集电极区域上方排列，收集区域。本征基层在凸起的收集器基座和介电层之上。外在基层在本征基层之上。因此，外部基极层和副集电极区域之间的空间增加。该增加的空间由电介质材料填充，并且本征基极层和次集电极区域之间的电连接由相对窄的未掺杂或低掺杂的升高的集电极基座提供。因此，集电极结电容减小，因此最大振荡频率增加。

3. 发明申请

US20130214275A1 TRANSISTOR HAVING A NARROW IN-SUBSTRATE COLLECTOR REGION FOR REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR 有权
标题翻译：具有用于减少基极集电极结电容的窄层内基板收集器区域的晶体管和形成晶体管的方法
公开(公告)号：US20130214275A1
公开(公告)日：2013-08-22
申请号：US13401064
申请日：2012-02-21
申请人： James W. Adkisson , David L. Harame , Qizhi Liu
发明人： James W. Adkisson , David L. Harame , Qizhi Liu
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/732 , H01L29/1004 , H01L29/66234 , H01L29/66242 , H01L29/7371
摘要： Disclosed are a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a narrow in-substrate collector region for reduced base-collector junction capacitance. The transistor has, within a substrate, a collector region positioned laterally adjacent to a trench isolation region. A relatively thin seed layer covers the trench isolation region and collector region. This seed layer has a monocrystalline center, which is aligned above and wider than the collector region (e.g., due to a solid phase epitaxy regrowth process), and a polycrystalline outer section. An intrinsic base layer is epitaxially deposited on the seed layer such that it similarly has a monocrystalline center section that is aligned above and wider than the collector region. An extrinsic base layer is the intrinsic base layer and has a monocrystalline extrinsic base-to-intrinsic base link-up region that is offset vertically from the collector region.
摘要翻译：公开了晶体管（例如，双极结型晶体管（BJT）或异质结双极晶体管（HBT））以及形成具有窄的衬底内集电极区域以减小基极 - 集电极结电容的晶体管的方法。晶体管在衬底内具有位于横向邻近沟槽隔离区域的集电极区域。相对薄的种子层覆盖沟槽隔离区域和收集器区域。该晶种层具有单晶中心，该晶体中心在集电极区域上方（例如由于固相外延再生长工艺）而上方且更宽，并且多晶外部部分。本征基底层外延沉积在种子层上，使得其类似地具有在集电极区域上方并且更宽的单晶中心部分。非本征基层是本征基层，并且具有从集电极垂直偏移的单晶非本征基本至本征基极连接区域。

4. 发明授权

US08786051B2 Transistor having a monocrystalline center section and a polycrystalline outer section, and narrow in-substrate collector region for reduced base-collector junction capacitance 有权
标题翻译：具有单晶中心部分和多晶外部部分的晶体管，以及用于降低的基极 - 集电极结电容的窄的衬底内集电极区域
公开(公告)号：US08786051B2
公开(公告)日：2014-07-22
申请号：US13401064
申请日：2012-02-21
申请人： James W. Adkisson , David L. Harame , Qizhi Liu
发明人： James W. Adkisson , David L. Harame , Qizhi Liu
IPC分类号： H01L21/02
CPC分类号： H01L29/732 , H01L29/1004 , H01L29/66234 , H01L29/66242 , H01L29/7371
摘要： Disclosed are a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a narrow in-substrate collector region for reduced base-collector junction capacitance. The transistor has, within a substrate, a collector region positioned laterally adjacent to a trench isolation region. A relatively thin seed layer covers the trench isolation region and collector region. This seed layer has a monocrystalline center, which is aligned above and wider than the collector region (e.g., due to a solid phase epitaxy regrowth process), and a polycrystalline outer section. An intrinsic base layer is epitaxially deposited on the seed layer such that it similarly has a monocrystalline center section that is aligned above and wider than the collector region. An extrinsic base layer is the intrinsic base layer and has a monocrystalline extrinsic base-to-intrinsic base link-up region that is offset vertically from the collector region.
摘要翻译：公开了晶体管（例如，双极结型晶体管（BJT）或异质结双极晶体管（HBT））以及形成具有窄的衬底内集电极区域以减小基极 - 集电极结电容的晶体管的方法。晶体管在衬底内具有位于横向邻近沟槽隔离区域的集电极区域。相对薄的种子层覆盖沟槽隔离区域和收集器区域。该晶种层具有单晶中心，该晶体中心在集电极区域上方（例如由于固相外延再生长工艺）而上方且更宽，并且多晶外部部分。本征基底层外延沉积在种子层上，使得其类似地具有在集电极区域上方并且更宽的单晶中心部分。非本征基层是本征基层，并且具有从集电极垂直偏移的单晶非本征基本至本征基极连接区域。

5. 发明申请

US20130134483A1 BIPOLAR TRANSISTOR WITH A RAISED COLLECTOR PEDASTAL FOR REDUCED CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR 有权
标题翻译：具有用于降低电容的集电器底座的双极晶体管和形成晶体管的方法
公开(公告)号：US20130134483A1
公开(公告)日：2013-05-30
申请号：US13307412
申请日：2011-11-30
申请人： James W. Adkisson , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
发明人： James W. Adkisson , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
IPC分类号： H01L29/737 , H01L21/331 , H01L29/73
CPC分类号： H01L29/66234 , H01L29/0826 , H01L29/66287 , H01L29/732 , H01L29/7371
摘要： Disclosed are a transistor and a method of forming the transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently, base-collector junction capacitance is reduced and, consequently, the maximum oscillation frequency is increased.
摘要翻译：公开了晶体管和以缩小的尺寸形成具有凸起的集电极基座的晶体管的方法，以减小基极 - 集电极结电容。凸起的收集器基座位于基板的顶表面上，垂直延伸穿过绝缘层（未掺杂或低掺杂）在衬底内的子集电极区域上方排列，收集区域。本征基层在凸起的收集器基座和介电层之上。外在基层在本征基层之上。因此，外部基极层和副集电极区域之间的空间增加。该增加的空间由电介质材料填充，并且本征基极层和次集电极区域之间的电连接由相对窄的未掺杂或低掺杂的升高的集电极基座提供。因此，集电极结电容减小，因此最大振荡频率增加。

6. 发明授权

US08723392B2 Saw filter having planar barrier layer and method of making 有权
标题翻译：具有平面阻挡层的锯片和制造方法
公开(公告)号：US08723392B2
公开(公告)日：2014-05-13
申请号：US13183977
申请日：2011-07-15
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC分类号： H03H9/25
CPC分类号： H03H9/14538 , H03H3/08
摘要： Disclosed herein is a surface acoustic wave (SAW) filter and method of making the same. The SAW filter includes a piezoelectric substrate; a planar barrier layer disposed above the piezoelectric substrate, and at least one conductor buried in the piezoelectric substrate and the planar barrier layer.
摘要翻译：本文公开了一种表面声波（SAW）滤波器及其制造方法。 SAW滤波器包括压电基片; 设置在所述压电基板上方的平面阻挡层，以及埋设在所述压电基板和所述平面阻挡层中的至少一个导体。

7. 发明授权

US08716771B2 Anti-reflection structures for CMOS image sensors 有权
公开(公告)号：US08716771B2
公开(公告)日：2014-05-06
申请号：US13418706
申请日：2012-03-13
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
IPC分类号： H01L31/10 , H01L31/112
CPC分类号： H01L31/103 , H01L24/05 , H01L24/73 , H01L27/14603 , H01L27/1462 , H01L27/14627 , H01L27/14629 , H01L27/1464 , H01L27/14643 , H01L31/02165 , H01L31/0236 , H01L2224/04042 , H01L2224/05 , H01L2224/32225 , H01L2224/48227 , H01L2224/48464 , H01L2224/4847 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/12043 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/3025 , Y02E10/50 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.

8. 发明授权

US08673683B2 Graphene field effect transistor 有权
标题翻译：石墨烯场效应晶体管
公开(公告)号：US08673683B2
公开(公告)日：2014-03-18
申请号：US13492131
申请日：2012-06-08
申请人： James W. Adkisson , Thomas J. Dunbar , Jeffrey P. Gambino , Molly J. Leitch , Edward J. Nowak
发明人： James W. Adkisson , Thomas J. Dunbar , Jeffrey P. Gambino , Molly J. Leitch , Edward J. Nowak
IPC分类号： H01L51/40 , H01L21/8232 , H01L21/336
CPC分类号： H01L29/1606 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/186 , H01L27/1222 , H01L29/41733 , H01L29/42384 , H01L29/66045 , H01L29/66742 , H01L29/778 , H01L29/7786 , H01L29/785 , H01L29/78684 , H01L29/78696
摘要： Manufacturing a semiconductor structure including: forming a seed material on an insulator layer; forming a graphene field effect transistor (FET) on the seed material; and forming an air gap under the graphene FET by removing the seed material.
摘要翻译：制造半导体结构，包括：在绝缘体层上形成种子材料; 在种子材料上形成石墨烯场效应晶体管（FET）; 并通过除去种子材料在石墨烯FET下方形成气隙。

9. 发明授权

US08409904B2 Methods for forming anti-reflection structures for CMOS image sensors 有权
标题翻译： CMOS图像传感器形成抗反射结构的方法
公开(公告)号：US08409904B2
公开(公告)日：2013-04-02
申请号：US13165375
申请日：2011-06-21
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
IPC分类号： H01L21/00
CPC分类号： H01L27/14685 , H01L27/14618 , H01L27/14625 , H01L27/14627 , H01L27/14632 , H01L27/14645 , H01L27/14689 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： Protuberances, having vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode, are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sublithographic features of a first polymeric block component within a matrix of a second polymeric block component. The pattern of the polymeric block component is transferred into a first optical layer to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.
摘要翻译：在具有不同折射率的两层之间的光学界面处形成具有小于由光电二极管可检测的光的波长范围的垂直和横向尺寸的突起。突起可以通过采用在第二聚合物嵌段组分的基质内形成第一聚合物嵌段组分的亚光刻特征阵列的自组装嵌段共聚物来形成。聚合物嵌段组分的图案被转移到第一光学层中以形成纳米级突起的阵列。或者，可以使用常规光刻来形成尺寸小于光的波长的突起。第二光学层直接形成在第一光学层的突起上。第一和第二光学层之间的界面具有渐变的折射率，并提供很少的反射光的高透射率。

10. 发明申请

US20130026646A1 PASSIVATED THROUGH WAFER VIAS IN LOW-DOPED SEMICONDUCTOR SUBSTRATES 有权
标题翻译：通过低压半导体衬底中的波形钝化
公开(公告)号：US20130026646A1
公开(公告)日：2013-01-31
申请号：US13193991
申请日：2011-07-29
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Alvin J. Joseph
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Alvin J. Joseph
IPC分类号： H01L21/28 , G06F17/50 , H01L23/48 , H01L21/22 , H01L21/265
CPC分类号： H01L21/76898 , H01L21/26586 , H01L29/732
摘要： A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate.
摘要翻译：用于形成钝化的晶片通孔的方法，通过晶片通孔结构钝化，并通过设计结构钝化通过晶片。该方法包括：在半导体衬底中形成贯穿晶片通孔，所述贯通晶片通孔包括从半导体衬底的顶部延伸到半导体衬底的底表面的电导体; 并且形成邻接电导体的所有侧壁的掺杂层，与半导体衬底相同的掺杂剂类型的掺杂层，掺杂层中掺杂剂的浓度大于半导体衬底中掺杂剂的浓度，掺杂层介于电导体和半导体衬底。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式