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1. 发明授权

US08927357B2 Junction field-effect transistor with raised source and drain regions formed by selective epitaxy 有权
标题翻译：通过选择性外延形成的具有升高的源极和漏极区的结场场效应晶体管
公开(公告)号：US08927357B2
公开(公告)日：2015-01-06
申请号：US13294731
申请日：2011-11-11
申请人： Kevin K. Chan , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
发明人： Kevin K. Chan , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
IPC分类号： H01L21/337 , H01L29/10 , H01L27/06 , H01L29/66 , H01L29/737 , H01L29/808 , H01L29/165 , H01L29/08
CPC分类号： H01L29/8086 , G06F17/5045 , H01L27/0623 , H01L29/0817 , H01L29/0826 , H01L29/1004 , H01L29/1058 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66242 , H01L29/66893 , H01L29/66901 , H01L29/732 , H01L29/7375 , H01L29/808
摘要： Junction field-effect transistors, methods for fabricating junction field-effect transistors, and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.
摘要翻译：结型场效应晶体管，用于制造结型场效应晶体管的方法，以及结型场效应晶体管的设计结构。结场效应晶体管的源极和漏极由通过选择性外延生长并与半导体层的顶表面直接接触的半导体材料组成。形成与在源极和漏极之间横向设置在半导体层中的沟道对准的栅极。源极，漏极和半导体层各自包括与包括栅极的第一半导体材料具有相反导电类型的第二半导体材料。

2. 发明申请

US20130119442A1 JUNCTION FIELD-EFFECT TRANSISTOR WITH RAISED SOURCE AND DRAIN REGIONS FORMED BY SELECTIVE EPITAXY 有权
标题翻译：具有选择性外延形成的上升源和漏区的连接场效应晶体管
公开(公告)号：US20130119442A1
公开(公告)日：2013-05-16
申请号：US13294731
申请日：2011-11-11
申请人： Kevin K. Chan , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
发明人： Kevin K. Chan , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
IPC分类号： H01L21/337 , G06F17/50 , H01L29/808
CPC分类号： H01L29/8086 , G06F17/5045 , H01L27/0623 , H01L29/0817 , H01L29/0826 , H01L29/1004 , H01L29/1058 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66242 , H01L29/66893 , H01L29/66901 , H01L29/732 , H01L29/7375 , H01L29/808
摘要： Junction field-effect transistors, methods for fabricating junction field-effect transistors, and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.
摘要翻译：结型场效应晶体管，用于制造结型场效应晶体管的方法，以及结型场效应晶体管的设计结构。结场效应晶体管的源极和漏极由通过选择性外延生长并与半导体层的顶表面直接接触的半导体材料组成。形成与在源极和漏极之间横向设置在半导体层中的沟道对准的栅极。源极，漏极和半导体层各自包括与包括栅极的第一半导体材料具有相反导电类型的第二半导体材料。

3. 发明申请

US20120228611A1 BIPOLAR JUNCTION TRANSISTOR WITH A SELF-ALIGNED EMITTER AND BASE 有权
标题翻译：具有自对准发射器和基极的双极性JUNCTION TRANSISTOR
公开(公告)号：US20120228611A1
公开(公告)日：2012-09-13
申请号：US13042902
申请日：2011-03-08
申请人： Kevin K. Chan , Erik M. Dahlstrom , Peter B. Gray , David L. Harame , Qizhi Liu
发明人： Kevin K. Chan , Erik M. Dahlstrom , Peter B. Gray , David L. Harame , Qizhi Liu
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/73 , H01L21/28518 , H01L29/0821 , H01L29/66272 , H01L29/732 , H01L29/7378
摘要： Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base.
摘要翻译：用于制造具有自对准发射极和非本征基极的双极结型晶体管的方法，通过该方法制造的双极结型晶体管以及用于BiCMOS集成电路的设计结构。使用牺牲发射器基座制造双极结型晶体管，该牺牲发射器基座提供牺牲的心轴，以促进发射极和外部基极之间的自对准。随后去除牺牲发射器基座以打开延伸到本征基底的发射器窗口。在发射器窗口中形成发射极，其位于本征基极上。

4. 发明授权

US08716096B2 Self-aligned emitter-base in advanced BiCMOS technology 失效
标题翻译：先进的BiCMOS技术中的自对准发射极基极
公开(公告)号：US08716096B2
公开(公告)日：2014-05-06
申请号：US13323977
申请日：2011-12-13
申请人： Kevin K. Chan , David L. Harame , Russell T. Herrin , Qizhi Liu
发明人： Kevin K. Chan , David L. Harame , Russell T. Herrin , Qizhi Liu
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/737 , H01L21/8249 , H01L27/0623 , H01L29/66242 , H01L29/66272 , H01L29/732 , H01L29/7371
摘要： A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot.
摘要翻译：公开了一种自对准双极晶体管及其制造方法。在一个实施例中，提供衬底和本征基极，随后是第一氧化物层，以及在第一氧化物层上的外部基极。形成第一开口，暴露外部基底的表面的一部分。在第一开口中形成侧壁间隔物，并且在外基的暴露表面上选择性地形成自对准氧化物掩模。去除间隔物，并且使用自对准氧化物掩模，暴露的非本征基底和第一氧化物层被蚀刻以暴露本征基底层，形成第一和第二狭槽。在第一和第二槽中的每一个中的暴露的本征和/或非本征基极层上选择性地生长硅层条纹，基本上填充相应的槽。

5. 发明授权

US08492237B2 Methods of fabricating a bipolar junction transistor with a self-aligned emitter and base 有权
标题翻译：制造具有自对准发射极和基极的双极结型晶体管的方法
公开(公告)号：US08492237B2
公开(公告)日：2013-07-23
申请号：US13042902
申请日：2011-03-08
申请人： Kevin K. Chan , Erik M. Dahlstrom , Peter B. Gray , David L. Harame , Qizhi Liu
发明人： Kevin K. Chan , Erik M. Dahlstrom , Peter B. Gray , David L. Harame , Qizhi Liu
IPC分类号： H01L21/8222
CPC分类号： H01L29/73 , H01L21/28518 , H01L29/0821 , H01L29/66272 , H01L29/732 , H01L29/7378
摘要： Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base.
摘要翻译：用于制造具有自对准发射极和非本征基极的双极结型晶体管的方法，通过该方法制造的双极结型晶体管以及用于BiCMOS集成电路的设计结构。使用牺牲发射器基座制造双极结型晶体管，该牺牲发射器基座提供牺牲的心轴，以促进发射极和外部基极之间的自对准。随后去除牺牲发射器基座以打开延伸到本征基底的发射器窗口。在发射器窗口中形成发射极，其位于本征基极上。

6. 发明申请

US20130146947A1 SELF-ALIGNED EMITTER-BASE IN ADVANCED BiCMOS TECHNOLOGY 失效
标题翻译：自制BiCMOS技术中的自对准发射体
公开(公告)号：US20130146947A1
公开(公告)日：2013-06-13
申请号：US13323977
申请日：2011-12-13
申请人： Kevin K. Chan , David L. Harame , Russell T. Herrin , Qizhi Liu
发明人： Kevin K. Chan , David L. Harame , Russell T. Herrin , Qizhi Liu
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/737 , H01L21/8249 , H01L27/0623 , H01L29/66242 , H01L29/66272 , H01L29/732 , H01L29/7371
摘要： A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot.
摘要翻译：公开了一种自对准双极晶体管及其制造方法。在一个实施例中，提供衬底和本征基极，随后是第一氧化物层，以及在第一氧化物层上的外部基极。形成第一开口，暴露外部基底的表面的一部分。在第一开口中形成侧壁间隔物，并且在外基的暴露表面上选择性地形成自对准氧化物掩模。去除间隔物，并且使用自对准氧化物掩模，暴露的非本征基底和第一氧化物层被蚀刻以暴露本征基底层，形成第一和第二狭槽。在第一和第二槽中的每一个中的暴露的本征和/或非本征基极层上选择性地生长硅层条纹，基本上填充相应的槽。

7. 发明授权

US08603883B2 Interface control in a bipolar junction transistor 失效
标题翻译：双极结晶体管中的接口控制
公开(公告)号：US08603883B2
公开(公告)日：2013-12-10
申请号：US13297464
申请日：2011-11-16
申请人： Kevin K. Chan , Peng Cheng , Qizhi Liu , Ljubo Radic
发明人： Kevin K. Chan , Peng Cheng , Qizhi Liu , Ljubo Radic
IPC分类号： H01L21/331
CPC分类号： H01L29/73 , G06F17/5045 , H01L29/1004 , H01L29/66272 , H01L29/7371
摘要： Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer.
摘要翻译：制造双极结型晶体管，双极结型晶体管以及双极结型晶体管的设计结构的方法。本征基底层的第一部分被掩蔽，同时蚀刻本征基底层的第二部分。作为掩蔽的结果，本征基底层的第二部分比本征基底层的第一部分薄。在与本征基层的第一和第二部分分别的接触关系中形成发射极和非本征基层。

8. 发明授权

US07037798B2 Bipolar transistor structure with self-aligned raised extrinsic base and methods 有权
标题翻译：双极晶体管结构具有自对准引出的外在基极和方法
公开(公告)号：US07037798B2
公开(公告)日：2006-05-02
申请号：US10904482
申请日：2004-11-12
申请人： Thomas N. Adam , Kevin K. Chan , Alvin J. Joseph , Marwan H. Khater , Qizhi Liu , Beth Ann Rainey , Kathryn T. Schonenberg
发明人： Thomas N. Adam , Kevin K. Chan , Alvin J. Joseph , Marwan H. Khater , Qizhi Liu , Beth Ann Rainey , Kathryn T. Schonenberg
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L29/1004 , H01L29/66242 , H01L29/66287
摘要： The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.
摘要翻译：本发明包括制造双极晶体管的方法，该双极晶体管在形成连接层之前，将硅锗（SiGe）层或例如高压氧化物（HIPOX）的第三绝缘体层与邻近本征基极的发射极帽顶上相加。该添加允许使用湿蚀刻化学去除连接层，以去除在不使用氧化的情况下形成在发射极帽顶上的多余SiGe或第三绝缘体层。在这种情况下，可以使用氧化物部分（通过沉积氧化物或上述HIPOX层的分离）和氮化物间隔物形成发射极 - 基极隔离。本发明导致较低的热循环，较低的应力水平和对发射极盖层厚度的更多控制，这是第一实施例的缺点。本发明还包括所得到的双极晶体管结构。

9. 发明申请

US20130119436A1 INTERFACE CONTROL IN A BIPOLAR JUNCTION TRANSISTOR 失效
公开(公告)号：US20130119436A1
公开(公告)日：2013-05-16
申请号：US13297464
申请日：2011-11-16
申请人： Kevin K. Chan , Peng Cheng , Qizhi Liu , Ljubo Radic
发明人： Kevin K. Chan , Peng Cheng , Qizhi Liu , Ljubo Radic
IPC分类号： H01L29/737 , G06F17/50 , H01L21/331
CPC分类号： H01L29/73 , G06F17/5045 , H01L29/1004 , H01L29/66272 , H01L29/7371
摘要： Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer.

10. 发明授权

US07119416B1 Bipolar transistor structure with self-aligned raised extrinsic base and methods 有权
公开(公告)号：US07119416B1
公开(公告)日：2006-10-10
申请号：US11169444
申请日：2005-06-29
申请人： Thomas N. Adam , Kevin K. Chan , Alvin J. Joseph , Marwan H. Khater , Qizhi Liu , Beth Ann Rainey , Kathryn T. Schonenberg
发明人： Thomas N. Adam , Kevin K. Chan , Alvin J. Joseph , Marwan H. Khater , Qizhi Liu , Beth Ann Rainey , Kathryn T. Schonenberg
IPC分类号： H01L27/82 , H01L29/70
CPC分类号： H01L29/7378 , H01L29/1004 , H01L29/66242 , H01L29/66287
摘要： The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.

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