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1. 发明授权

US06836003B2 Integrated circuit package alignment feature 失效
标题翻译：集成电路封装对准功能
公开(公告)号：US06836003B2
公开(公告)日：2004-12-28
申请号：US09819874
申请日：2001-03-28
申请人： David J. Corisis , Tracy Reynolds , Michael Slaughter , Daniel Cram , Leland R. Nevill , Jerrold L. King
发明人： David J. Corisis , Tracy Reynolds , Michael Slaughter , Daniel Cram , Leland R. Nevill , Jerrold L. King
IPC分类号： H01L23495
CPC分类号： G01R31/2851 , G01R1/0408 , G01R31/2884 , H01L23/4951 , H01L23/544 , H01L24/48 , H01L24/49 , H01L2223/54473 , H01L2223/54486 , H01L2224/05554 , H01L2224/05599 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H05K3/303 , H05K2201/10568 , H05K2201/10689 , H05K2201/10696 , H05K2203/167 , Y02P70/613 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2924/00012
摘要： An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature includes a cut out on the lead frame taking the form of a semicircle, protuberance, apertures, or slots. Alternatively, the alignment feature includes a removably coupled tab. After testing of the integrated circuit has been completed, the alignment tab is removed from the integrated circuit. The alignment feature can also be provided on a heat spreader which is attached to a side of or within the lead frame package.
摘要翻译：提供了具有与引线框一体的对准特征的集成电路。集成电路包括与半导体管芯耦合的引线框架，并部分封装在绝缘材料中。引线框架具有其中的对准特征。对准特征包括在引线框架上切割出半圆形，突起，孔或槽的形式。或者，对准特征包括可移除地耦合的突片。集成电路测试完成后，对准标签从集成电路中取出。对准特征也可以设置在附着于引线框架封装的一侧或内部的散热器上。

2. 发明授权

US06246108B1 Integrated circuit package including lead frame with electrically isolated alignment feature 有权
标题翻译：集成电路封装，包括带电隔离对准功能的引线框架
公开(公告)号：US06246108B1
公开(公告)日：2001-06-12
申请号：US09374176
申请日：1999-08-12
申请人： David J. Corisis , Tracy Reynolds , Michael Slaughter , Daniel Cram , Leland R. Nevill , Jerrold L. King
发明人： David J. Corisis , Tracy Reynolds , Michael Slaughter , Daniel Cram , Leland R. Nevill , Jerrold L. King
IPC分类号： H01L2348
CPC分类号： G01R31/2851 , G01R1/0408 , G01R31/2884 , H01L23/4951 , H01L23/544 , H01L24/48 , H01L24/49 , H01L2223/54473 , H01L2223/54486 , H01L2224/05554 , H01L2224/05599 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H05K3/303 , H05K2201/10568 , H05K2201/10689 , H05K2201/10696 , H05K2203/167 , Y02P70/613 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2924/00012
摘要： An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature includes a cut out on the lead frame taking the form of a semi-circle, protuberance, apertures, or slots. Alternatively, the alignment feature includes a removably coupled tab. After testing of the integrated circuit has been completed, the alignment tab is removed from the integrated circuit. The alignment feature can also be provided on a heat spreader which is attached to a side of or within the lead frame package.
摘要翻译：提供了具有与引线框一体的对准特征的集成电路。集成电路包括与半导体管芯耦合的引线框架，并部分封装在绝缘材料中。引线框架具有其中的对准特征。对准特征包括在引线框架上切割成半圆形，突起，孔或槽的形式。或者，对准特征包括可移除地耦合的突片。集成电路测试完成后，对准标签从集成电路中取出。对准特征也可以设置在附着于引线框架封装的一侧或内部的散热器上。

3. 发明授权

US6048744A Integrated circuit package alignment feature 失效
标题翻译：集成电路封装对准功能
公开(公告)号：US6048744A
公开(公告)日：2000-04-11
申请号：US929843
申请日：1997-09-15
申请人： David J. Corisis , Tracy Reynolds , Michael Slaughter , Daniel Cram , Leland R. Nevill , Jerrold L. King
发明人： David J. Corisis , Tracy Reynolds , Michael Slaughter , Daniel Cram , Leland R. Nevill , Jerrold L. King
IPC分类号： G01R1/04 , G01R31/28 , H01L23/495 , H01L23/544 , H05K3/30 , G01R31/26 , H01L21/44 , H01L21/48 , H01L21/50 , H01L21/66
CPC分类号： G01R31/2851 , H01L23/4951 , H01L23/544 , H05K3/303 , G01R1/0408 , G01R31/2884 , H01L2223/54473 , H01L2223/54486 , H01L2224/05554 , H01L2224/05599 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/85399 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H05K2201/10568 , H05K2201/10689 , H05K2201/10696 , H05K2203/167 , Y02P70/613
摘要： An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature includes a cut out on the lead frame taking the form of a semi-circle, protuberance, apertures, or slots. Alternatively, the alignment feature includes a removably coupled tab. After testing of the integrated circuit has been completed, the alignment tab is removed from the integrated circuit. The alignment feature can also be provided on a heat spreader which is attached to a side of or within the lead frame package.
摘要翻译：提供了具有与引线框一体的对准特征的集成电路。集成电路包括与半导体管芯耦合的引线框架，并部分封装在绝缘材料中。引线框架具有其中的对准特征。对准特征包括在引线框架上切割成半圆形，突起，孔或槽的形式。或者，对准特征包括可移除地耦合的突片。集成电路测试完成后，对准标签从集成电路中取出。对准特征也可以设置在附着于引线框架封装的一侧或内部的散热器上。

4. 发明授权

US06682946B2 Method of using a semiconductor chip package 有权
标题翻译：使用半导体芯片封装的方法
公开(公告)号：US06682946B2
公开(公告)日：2004-01-27
申请号：US10119461
申请日：2002-04-10
申请人： Jerrold L. King , Leland R. Nevill
发明人： Jerrold L. King , Leland R. Nevill
IPC分类号： H01L2166
CPC分类号： H05K3/303 , G01R31/2851 , G01R31/2884 , H05K2201/10568 , H05K2201/10689 , H05K2203/0195 , Y02P70/613
摘要： An improved semiconductor chip package capable of independently aligning with testing equipment during the manufacturing phase of electrical testing. Independent alignment is realized by directly connecting the semiconductor chip package to the test alignment apparatus by fitting together two substantially conforming surfaces, one on the chip package and one on the alignment apparatus. The conforming surfaces are arranged so that only one matable position is achievable. The substantially conforming surfaces equate to three substantially conical indentations on the chip package and three substantially conical protrusions or protuberances of substantially conforming size and depth extending from the alignment apparatus. Once fitted, the three protrusions suspend the semiconductor chip in a substantially horizontal plane so that electrical test contacts, also substantially in a horizontal plane, may be easily contacted with the conductive leads extending generally horizontally and co-planar from the semiconductor chip.
摘要翻译：改进的半导体芯片封装，能够在电气测试制造阶段与测试设备独立对齐。通过将两个基本上一致的表面（一个在芯片封装上）和一个在对准装置上装配在一起，将半导体芯片封装直接连接到测试对准装置，实现独立对准。配合表面被布置成仅可实现一个可配合的位置。基本上一致的表面等同于芯片封装上的三个基本上圆锥形的凹口，以及从对准装置延伸的基本上一致的尺寸和深度的三个基本上圆锥形的突起或突起。一旦安装，三个突起将半导体芯片悬挂在基本上水平的平面中，使得电测试接触（也基本上在水平面）可以容易地与从半导体芯片大致水平并共面延伸的导电引线接触。

5. 发明授权

US06670720B2 Semiconductor chip package with alignment structure 有权
标题翻译：半导体芯片封装
公开(公告)号：US06670720B2
公开(公告)日：2003-12-30
申请号：US09799179
申请日：2001-03-05
申请人： Jerrold L. King , Leland R. Nevill
发明人： Jerrold L. King , Leland R. Nevill
IPC分类号： H01L2348
CPC分类号： H05K3/303 , G01R31/2851 , G01R31/2884 , H05K2201/10568 , H05K2201/10689 , H05K2203/0195 , Y02P70/613
摘要： An improved semiconductor chip package capable of independently aligning with testing equipment during the manufacturing phase of electrical testing. Independent alignment is realized by directly connecting the semiconductor chip package to the test alignment apparatus by fitting together two substantially conforming surfaces, one on the chip package and one on the alignment apparatus. The conforming surfaces are arranged so that only one matable position is achievable. The substantially conforming surfaces can equate to three substantially conical indentations on the chip package and three substantially conical protrusions or protuberances of substantially conforming size and depth extending from the alignment apparatus. Once fitted, the three protrusions suspend the semiconductor chip in a substantially horizontal plane so that electrical test contacts, also substantially in a horizontal plane, may be easily contacted with the conductive leads extending generally horizontally and co-planar from the semiconductor chip.
摘要翻译：改进的半导体芯片封装，能够在电气测试制造阶段与测试设备独立对齐。通过将两个基本上一致的表面（一个在芯片封装上）和一个在对准装置上装配在一起，将半导体芯片封装直接连接到测试对准装置，实现独立对准。配合表面被布置成仅可实现一个可配合的位置。基本上一致的表面可以等同于芯片封装上的三个基本上圆锥形的凹口，以及从对准装置延伸的基本上一致的尺寸和深度的三个基本上圆锥形的突起或突起。一旦安装，三个突起将半导体芯片悬挂在基本上水平的平面中，使得电测试接触（也基本上在水平面）可以容易地与从半导体芯片大致水平并共面延伸的导电引线接触。

6. 发明授权

US06198172B1 Semiconductor chip package 失效
标题翻译：半导体芯片封装
公开(公告)号：US06198172B1
公开(公告)日：2001-03-06
申请号：US09026584
申请日：1997-02-20
申请人： Jerrold L. King , Leland R. Nevill
发明人： Jerrold L. King , Leland R. Nevill
IPC分类号： H01L23544
CPC分类号： H05K3/303 , G01R31/2851 , G01R31/2884 , H05K2201/10568 , H05K2201/10689 , H05K2203/0195 , Y02P70/613
摘要： An improved semiconductor chip package capable of independently aligning with testing equipment during the manufacturing phase of electrical testing. Independent alignment is realized by directly connecting the semiconductor chip package to the test alignment apparatus by fitting together two substantially conforming surfaces, one on the chip package and one on the alignment apparatus. The conforming surfaces are arranged so that only one matable position is achievable. The substantially conforming surfaces equate to three substantially conical indentations on the chip package and three substantially conical protrusions or protuberances of substantially conforming size and depth extending from the alignment apparatus. Once fitted, the three protrusions suspend the semiconductor chip in a substantially horizontal plane so that electrical test contacts, also substantially in a horizontal plane, may be easily contacted with the conductive leads extending generally horizontally and co-planar from the semiconductor chip.
摘要翻译：改进的半导体芯片封装，能够在电气测试制造阶段与测试设备独立对齐。通过将两个基本上一致的表面（一个在芯片封装上）和一个在对准装置上装配在一起，将半导体芯片封装直接连接到测试对准装置，实现独立对准。配合表面被布置成仅可实现一个可配合的位置。基本上一致的表面等同于芯片封装上的三个基本上圆锥形的凹口，以及从对准装置延伸的基本上一致的尺寸和深度的三个基本上圆锥形的突起或突起。一旦安装，三个突起将半导体芯片悬挂在基本上水平的平面中，使得电测试接触（也基本上在水平面）可以容易地与从半导体芯片大致水平并共面延伸的导电引线接触。

7. 发明授权

US06420195B1 Method of aligning and testing a semiconductor chip package 有权
标题翻译：半导体芯片封装对准和测试方法
公开(公告)号：US06420195B1
公开(公告)日：2002-07-16
申请号：US09190545
申请日：1998-11-12
申请人： Jerrold L. King , Leland R. Nevill
发明人： Jerrold L. King , Leland R. Nevill
IPC分类号： G01R3126
CPC分类号： H05K3/303 , G01R31/2851 , G01R31/2884 , H05K2201/10568 , H05K2201/10689 , H05K2203/0195 , Y02P70/613
摘要： An improved semiconductor chip package capable of independently aligning with testing equipment during the manufacturing phase of electrical testing. Independent alignment is realized by directly connecting the semiconductor chip package to the test alignment apparatus by fitting together two substantially conforming surfaces, one on the chip package and one on the alignment apparatus. The conforming surfaces are arranged so that only one matable position is achievable. The substantially conforming surfaces equate to three substantially conical indentations on the chip package and three substantially hemispherical protrusions or protuberances of substantially conforming size and depth extending from the alignment apparatus. Once fitted, the three protrusions suspend the semiconductor chip in a substantially horizontal plane so that electrical test contacts, also substantially in a horizontal plane, may be easily contacted with the conductive leads extending generally horizontally and co-planar from the semiconductor chip.
摘要翻译：改进的半导体芯片封装，能够在电气测试制造阶段与测试设备独立对齐。通过将两个基本上一致的表面（一个在芯片封装上）和一个在对准装置上装配在一起，将半导体芯片封装直接连接到测试对准装置，实现独立对准。配合表面被布置成仅可实现一个可配合的位置。基本上一致的表面等于芯片封装上的三个基本上圆锥形的凹陷，以及从对准装置延伸的基本上一致的尺寸和深度的三个基本上半球形的突起或突起。一旦安装，三个突起将半导体芯片悬挂在基本上水平的平面中，使得电测试接触（也基本上在水平面）可以容易地与从半导体芯片大致水平并共面延伸的导电引线接触。

8. 发明授权

US5872398A Reduced stress LOC assembly including cantilevered leads 失效
标题翻译：减少应力LOC组件，包括悬臂引线
公开(公告)号：US5872398A
公开(公告)日：1999-02-16
申请号：US584738
申请日：1996-01-11
申请人： Jerrold L. King , Larry D. Kinsman , Jerry M. Brooks , David J. Corisis
发明人： Jerrold L. King , Larry D. Kinsman , Jerry M. Brooks , David J. Corisis
IPC分类号： H01L23/495 , H01L23/48
CPC分类号： H01L24/06 , H01L23/4951 , H01L24/05 , H01L2224/04042 , H01L2224/05556 , H01L2224/05599 , H01L2224/06136 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/48647 , H01L2224/48699 , H01L2224/48747 , H01L2224/73215 , H01L2224/85447 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181
摘要： An LOC die assembly including a die dielectrically adhered to the underside of a lead frame. The adhesive is applied over a minimum cross-sectional area and number of attachment points to maximize flexure of leads extending over the active surface of the die. In this manner, flexure of the leads to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant is maximized, and the point stresses on the active surface caused by the filler particles are reduced by the lead flexure.
摘要翻译：一个LOC模具组件，其包括一个介电粘附到引线框架下侧的模具。将粘合剂施加在最小横截面面积和附着点的数量上，以使引线在模具的有效表面上延伸的弯曲最大化。以这种方式，使塑料密封剂的传递模塑期间引线的挠曲适应填充在引线和模具的有效表面之间的填料颗粒，由填料颗粒引起的活性表面上的点应力减小导线弯曲。

9. 发明授权

US06590277B1 Reduced stress LOC assembly 失效
标题翻译：减少应力LOC装配
公开(公告)号：US06590277B1
公开(公告)日：2003-07-08
申请号：US09505058
申请日：2000-02-16
申请人： Jerrold L. King , Larry D. Kinsman , Jerry M. Brooks , David J. Corisis
发明人： Jerrold L. King , Larry D. Kinsman , Jerry M. Brooks , David J. Corisis
IPC分类号： H01L23495
CPC分类号： H01L24/06 , H01L23/4951 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05556 , H01L2224/05599 , H01L2224/06136 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/48647 , H01L2224/48699 , H01L2224/48747 , H01L2224/73215 , H01L2224/85447 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/00 , H01L2924/00012
摘要： An LOC die assembly including a die dielectrically adhered to the under of lead frame. The adhesive is applied over a minimum cross-sectional area and number of attachment points to maximize flexure of leads extending over the active surface of the die. In this manner, flexure of the leads to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant is maximized, and the point stresses on the active surface caused by the filler particles are reduced by the lead flexure.
摘要翻译：一个LOC模具组件，其包括一个介电粘附到引线框架下面的模具。将粘合剂施加在最小横截面面积和附着点的数量上，以使引线在模具的有效表面上延伸的弯曲最大化。以这种方式，使塑料密封剂的传递模塑期间引线的挠曲适应填充在引线和模具的有效表面之间的填料颗粒，由填料颗粒引起的活性表面上的点应力减小导线弯曲。

10. 发明授权

US6083777A Reduced stress LOC assembly 有权
公开(公告)号：US6083777A
公开(公告)日：2000-07-04
申请号：US416369
申请日：1999-10-12
申请人： Jerrold L. King , Larry D. Kinsman , Jerry M. Brooks , David J. Corisis
发明人： Jerrold L. King , Larry D. Kinsman , Jerry M. Brooks , David J. Corisis
IPC分类号： H01L23/495 , H01L21/50
CPC分类号： H01L24/06 , H01L23/4951 , H01L24/05 , H01L2224/04042 , H01L2224/05556 , H01L2224/05599 , H01L2224/06136 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/48647 , H01L2224/48699 , H01L2224/48747 , H01L2224/73215 , H01L2224/85447 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181
摘要： An LOC die assembly including a die dielectrically adhered to the underside of a lead frame. The adhesive is applied over a minimum cross-sectional area and number of attachment points to maximize flexure of leads extending over the active surface of the die. In this manner, flexure of the leads to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant is maximized, and the point stresses on the active surface caused by the filler particles are reduced by the lead flexure.

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