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1. 发明授权

US07088008B2 Electronic package with optimized circuitization pattern 失效
标题翻译：电子封装具有优化的电路图案
公开(公告)号：US07088008B2
公开(公告)日：2006-08-08
申请号：US10392617
申请日：2003-03-20
申请人： David J. Alcoe , William Infantolino , Virendra R. Jadhav
发明人： David J. Alcoe , William Infantolino , Virendra R. Jadhav
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/49838 , H01L23/49811 , H01L23/49822 , H01L2224/16225 , H01L2224/73253 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/15312 , H01L2924/16195 , H05K1/113 , H05K1/114 , H05K1/115 , H05K1/116 , H05K3/3426 , H05K3/4602 , H05K2201/09454 , H05K2201/09472 , H05K2201/09509 , H05K2201/0979 , H05K2201/10318 , Y10T29/49149 , H01L2224/0401
摘要： An electronic package, such as a chip carrier, with an optimized circuit pattern having a circuitized substrate with a first and second circuit pattern is provided. The circuitized substrate includes a corner surface region. The second circuit pattern is electrically connected to the first circuit pattern on the corner surface region of the circuitized substrate and is positioned in such a manner so as to substantially inhibit cracking of the first circuit pattern during flexure of the chip carrier.
摘要翻译：提供具有电路图案的具有第一和第二电路图案的电路化基板的具有优化的电路图案的诸如芯片载体的电子封装。电路化基板包括拐角表面区域。第二电路图案电连接到电路化基板的角表面区域上的第一电路图案，并且以这样的方式定位，以便在芯片载体弯曲期间基本上抑制第一电路图案的破裂。

2. 发明授权

US06759270B2 Semiconductor chip module and method of manufacture of same 失效
公开(公告)号：US06759270B2
公开(公告)日：2004-07-06
申请号：US10660261
申请日：2003-09-11
申请人： William Infantolino , Voya R. Markovich , Sanjeev B. Sathe , George H. Thiel
发明人： William Infantolino , Voya R. Markovich , Sanjeev B. Sathe , George H. Thiel
IPC分类号： H01L2144
CPC分类号： H01L24/19 , H01L23/5389 , H01L24/24 , H01L25/0655 , H01L2224/04105 , H01L2224/20 , H01L2224/24137 , H01L2224/24227 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/00
摘要： A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.

3. 发明授权

US06747331B2 Method and packaging structure for optimizing warpage of flip chip organic packages 有权
公开(公告)号：US06747331B2
公开(公告)日：2004-06-08
申请号：US10197335
申请日：2002-07-17
申请人： William Infantolino , Li Li , Steven G. Rosser , Sanjeev Balwant Sathe
发明人： William Infantolino , Li Li , Steven G. Rosser , Sanjeev Balwant Sathe
IPC分类号： H01L3100
CPC分类号： H01L23/49838 , H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H01L2924/01029 , H01L2924/10253 , H01L2924/12044 , H01L2924/15311 , H01L2924/3511 , H01L2924/00 , H01L2224/0401
摘要： An electronic packaging structure and method of forming thereof wherein the structure is constituted of a modular arrangement which reduces stresses generated in a chip, underfill, and ball grid array connection with a flexible substrate in the form of an organic material, which stresses may result in potential delamination due to thermally-induced warpage between the components of the modular arrangement.

4. 发明授权

US06433283B1 Dual purpose ribbon cable 有权
公开(公告)号：US06433283B1
公开(公告)日：2002-08-13
申请号：US09860549
申请日：2001-05-21
申请人： William L. Brodsky , David V. Caletka , William Infantolino
发明人： William L. Brodsky , David V. Caletka , William Infantolino
IPC分类号： H01B708
摘要： A ribbon cable includes electrical conductors surrounded by an insulator and vent tubes positioned adjacent and parallel to the conductors and insulator. The vent tubes allow airflow between an internal area of the enclosure and an external atmosphere and prevent access to the internal area of the enclosure.

5. 发明授权

US06905961B2 Land grid array stiffener for use with flexible chip carriers 失效
标题翻译：用于柔性芯片载体的土地格栅阵列加强筋
公开(公告)号：US06905961B2
公开(公告)日：2005-06-14
申请号：US10336579
申请日：2003-01-03
申请人： David Vincent Caletka , Krishna Darbha , William Infantolino , Eric Arthur Johnson
发明人： David Vincent Caletka , Krishna Darbha , William Infantolino , Eric Arthur Johnson
IPC分类号： H01L23/498 , H01L21/44
CPC分类号： H01L23/4985 , H01L2224/16 , H01L2924/01087 , H01L2924/10253 , H01L2924/15311 , H01L2924/16195 , H01L2924/00
摘要： A flexible chip carrier with contact pads on its upper surface matching those of the chip with said pads conductively connected to land grid array (LGA) pads on its lower surface matching the those of a card or PCB. The chip carrier is provided with a stiffening layer at the LGA interface. The stiffening layer is mechanically attached to the lower surface of the chip carrier. Holes are formed in the stiffening layer to expose the LGA pads. The holes are then filled with a conductive adhesive material. Compliant LGA bumps are applied to the uncured conductive adhesive material which material is then cured.
摘要翻译：具有在其上表面上具有接触焊盘的柔性芯片载体，其与所述芯片的接触焊盘匹配，所述焊盘导电地连接到其下表面上与卡或PCB匹配的焊盘格栅阵列（LGA）焊盘。芯片载体在LGA接口处设有加强层。加强层机械地附接到芯片载体的下表面。在加强层中形成孔以暴露LGA垫。然后用导电粘合剂材料填充孔。对未固化的导电粘合剂材料施加合适的LGA凸块，该材料然后被固化。

6. 发明授权

US06756662B2 Semiconductor chip module and method of manufacture of same 有权
公开(公告)号：US06756662B2
公开(公告)日：2004-06-29
申请号：US10254414
申请日：2002-09-25
申请人： William Infantolino , Voya R. Markovich , Sanjeev B. Sathe , George H. Thiel
发明人： William Infantolino , Voya R. Markovich , Sanjeev B. Sathe , George H. Thiel
IPC分类号： H01L2302
CPC分类号： H01L24/19 , H01L23/5389 , H01L24/24 , H01L25/0655 , H01L2224/04105 , H01L2224/20 , H01L2224/24137 , H01L2224/24227 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/00
摘要： A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.

7. 发明授权

US6014031A Apparatus for pressing an electronic card against contacts of a test socket 失效
标题翻译：用于将电子卡抵抗测试插座的触点的装置
公开(公告)号：US6014031A
公开(公告)日：2000-01-11
申请号：US762790
申请日：1996-12-10
申请人： William Infantolino
发明人： William Infantolino
IPC分类号： G01R31/28 , G01R31/02
CPC分类号： G01R31/2808
摘要： A test structure tests an electronic card having electrical contacts on one face and a chip on the other face. By way of example, the electrical contacts on the card comprise an array of solder balls. The structure comprises a socket for receiving the card such that the electrical contacts of the card face electrical contacts within the socket. The structure further comprises a plate, received over the socket and having at least two ribs which protrude downwardly from one face of the plate and are positioned over the socket to engage a center portion of the chip when the card is received in the socket. The plate also has at least two holes. One of the ribs is positioned between the two holes but does not surround either of the holes. Consequently, forced air can flow downwardly through the holes in the plate, horizontally between the plate and the chip and out of the test structure. Preferably, the two ribs cross each other, and there are four holes in the plate which are arranged in four respective quadrants defined by the cross.
摘要翻译：测试结构测试在一个面上具有电触点和另一个面上的芯片的电子卡。作为示例，卡上的电触点包括焊球阵列。该结构包括用于接收卡的插座，使得卡的电触点在插座内电接触。该结构还包括一个板，容纳在该插座上，并且具有至少两个从板的一个表面向下突出的肋，并且当卡被接纳在插座中时位于插座上方以接合芯片的中心部分。该板还具有至少两个孔。其中一个肋位于两个孔之间，但不围绕任何一个孔。因此，强制空气可以通过板中的孔向下流动，在板和芯片之间水平地离开测试结构。优选地，两个肋彼此交叉，并且板中有四个孔布置在由十字架限定的四个相应的象限中。

8. 发明授权

US07026706B2 Method and packaging structure for optimizing warpage of flip chip organic packages 失效
标题翻译：用于优化倒装芯片有机封装翘曲的方法和封装结构
公开(公告)号：US07026706B2
公开(公告)日：2006-04-11
申请号：US10771728
申请日：2004-02-04
申请人： William Infantolino , Li Li , Steven G. Rosser , Sanjeev Balwant Sathe
发明人： William Infantolino , Li Li , Steven G. Rosser , Sanjeev Balwant Sathe
IPC分类号： H01L23/48
CPC分类号： H01L23/49838 , H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H01L2924/01029 , H01L2924/10253 , H01L2924/12044 , H01L2924/15311 , H01L2924/3511 , H01L2924/00 , H01L2224/0401
摘要： An electronic packaging structure and method of forming thereof wherein the structure is constituted of a modular arrangement which reduces stresses generated in a chip, underfill, and ball grid array connection with a flexible substrate in the form of an organic material, which stresses may result in potential delamination due to thermally-induced warpage between the components of the modular arrangement.
摘要翻译：一种电子封装结构及其形成方法，其中该结构由模块化布置构成，该模块布置减少了以有机材料形式的柔性基板的芯片，底部填充和球栅阵列连接中产生的应力，该应力可导致由于模块化布置的组件之间的热引起的翘曲引起的潜在的分层。

9. 发明授权

US06967389B2 Wafer with semiconductor chips mounted thereon 失效
标题翻译：具有安装在其上的半导体芯片的晶片
公开(公告)号：US06967389B2
公开(公告)日：2005-11-22
申请号：US10744368
申请日：2003-12-23
申请人： William Infantolino , Voya R. Markovich , Sanjeev B. Sathe , George H. Thiel
发明人： William Infantolino , Voya R. Markovich , Sanjeev B. Sathe , George H. Thiel
IPC分类号： H01L23/538 , H01L25/065 , H01L23/58
CPC分类号： H01L24/19 , H01L23/5389 , H01L24/24 , H01L25/0655 , H01L2224/04105 , H01L2224/20 , H01L2224/24137 , H01L2224/24227 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/00
摘要： A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.
摘要翻译：提供了一种半导体芯片模块和形成方法。模块包括具有至少一个开口以容纳半导体芯片的阱的支撑构件。每个阱深度基本上等于芯片的厚度。支撑构件具有围绕每个孔的平面区域。一个芯片在每个井。绝缘片材料层叠在每个芯片上并延伸到围绕阱的平面区域上并具有远离芯片的面。包括捕获垫的电路形成在电介质片的表面上并延伸到覆盖在平面区域上的片上。导电通孔形成在将电介质片上的电路与芯片上的接触焊盘连接的电介质片中。将具有扇出图案的多层电路叠层体叠层在电介质片上。

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