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1. 发明授权

US5909130A Digital lock detector for phase-locked loop 失效
标题翻译：数字锁定检测器，用于锁相环
公开(公告)号：US5909130A
公开(公告)日：1999-06-01
申请号：US837244
申请日：1997-04-10
申请人： David G. Martin , Scott Wayne McLellan
发明人： David G. Martin , Scott Wayne McLellan
IPC分类号： H03L7/089 , H03L7/095 , H03L7/08
CPC分类号： H03L7/095 , H03L7/089
摘要： A phase lock detector circuit is disclosed that generates delayed versions of both a reference clock signal and a synthesized clock signal. From the delayed signals, first and second control signals that are pulses are generated. The pulses are passed through respective delays of predetermined durations and then clocked into respective shift registers by the latched signal of the opposite input. The shift register outputs are logically combined and shifted into a third shift register. Outputs from the third shift register are logically combined to ascertain whether a phase-lock loop is phase lock. The lock detector circuit may include a lock-out circuit to disable the phase lock detector circuit upon detecting phase lock.
摘要翻译：公开了一种产生参考时钟信号和合成时钟信号的延迟版本的锁相检测器电路。从延迟信号中，产生作为脉冲的第一和第二控制信号。脉冲通过预定持续时间的相应延迟，然后通过相对输入的锁存信号计时到相应的移位寄存器。移位寄存器输出逻辑组合并移入第三移位寄存器。逻辑上组合来自第三移位寄存器的输出，以确定锁相环是锁相。锁定检测器电路可以包括锁定电路，以在检测到相位锁定时禁止锁相检测器电路。

2. 发明授权

US6127860A Linear expansion based sine generator 失效
标题翻译：基于线性膨胀的正弦发生器
公开(公告)号：US6127860A
公开(公告)日：2000-10-03
申请号：US971430
申请日：1997-11-17
申请人： David G. Martin , Xiao-an Wang
发明人： David G. Martin , Xiao-an Wang
IPC分类号： G06F1/035 , H03B21/00
CPC分类号： G06F1/0356 , G06F2101/04
摘要： An apparatus and method for generating a sine wave signal for a desired phase input. The sine wave signal is generated by implementing a linear expansion of the sine function. An incoming phase value is divided into a base phase value and an incremental phase value. The sine value for each base phase value is stored in a look-up table. The sine values for phase values falling between base phase values are generated using a linear expansion of the sine function.
摘要翻译：一种用于产生所需相位输入的正弦波信号的装置和方法。通过实现正弦函数的线性扩展来产生正弦波信号。输入相位值被分为基相位值和增量相位值。每个基相位值的正弦值存储在查找表中。使用正弦函数的线性扩展产生落在基相位值之间的相位值的正弦值。

3. 发明授权

US5553121A Voice response system 失效
标题翻译：语音应答系统
公开(公告)号：US5553121A
公开(公告)日：1996-09-03
申请号：US467328
申请日：1995-06-06
申请人： David G. Martin , Lawrence L. Porter
发明人： David G. Martin , Lawrence L. Porter
IPC分类号： G06F3/16 , H04M3/493 , H04M3/50 , H04M3/00
CPC分类号： H04M3/493
摘要： The present invention relates to system for varying the voice menus and segments presented to the user of a voice response system according to the competence of the user. The response time of a user to voice prompts is measured and an average response time is determined. It is assumed that the lower the average response time, the greater the competence of the user. The average response time is used as an index to a table of ranges of response times. Each range has respective voice segments associated therewith. The voice segments comprise oral instructions or queries for the user and vary according to the anticipated competence of the user. If the average response time changes such that the voice segments indexed are different to the current voice segments then a data base containing information relating to user competence is updated to reflect such a change. Accordingly, when the user next interacts with the voice response system a new set of voice segments more appropriate to the user's competence with be played.
摘要翻译：本发明涉及根据用户的能力改变呈现给语音应答系统的用户的语音菜单和段的系统。测量用户对语音提示的响应时间，并确定平均响应时间。假设平均响应时间越短，用户的能力越强。平均响应时间用作响应时间范围表的索引。每个范围具有与其相关联的相应语音段。语音段包括对用户的口头指令或查询，并且根据用户的预期能力而变化。如果平均响应时间改变，使得索引的语音片段与当前语音片段不同，则包含与用户能力有关的信息的数据库被更新以反映这种改变。因此，当用户接下来与语音响应系统进行交互时，可以播放更适合用户能力的一组新的语音段。

4. 发明授权

US07834634B2 Low-power switch state detection circuit and method and mobile telephone incorporating the same 有权
标题翻译：低功耗开关状态检测电路和方法以及并入其中的移动电话
公开(公告)号：US07834634B2
公开(公告)日：2010-11-16
申请号：US11123569
申请日：2005-05-06
申请人： David G. Martin , Richard Verney , Robert W. Walden
发明人： David G. Martin , Richard Verney , Robert W. Walden
IPC分类号： G01R31/02 , G01R31/327 , H01H31/10
CPC分类号： H01H9/167 , H03K17/18 , Y10T307/76
摘要： A circuit for, and method of, detecting a signal level on a node and a mobile telephone device incorporating the circuit or the method. In one embodiment, the circuit includes: (1) a switch coupled between a voltage source and the node, (2) a pulse generator coupled to the switch and configured to generate a pulse to control the switch and (3) a detection circuit coupled to the node and configured to detect a signal level at the node on closure of the switch.
摘要翻译：用于检测节点上的信号电平的电路和方法以及结合该电路或方法的移动电话设备。在一个实施例中，电路包括：（1）耦合在电压源和节点之间的开关，（2）脉冲发生器，耦合到开关并被配置为产生脉冲以控制开关，以及（3）耦合的检测电路并且被配置为在开关闭合时检测节点处的信号电平。

5. 发明授权

US06525394B1 Substrate isolation for analog/digital IC chips 有权
标题翻译：模拟/数字IC芯片的基板隔离
公开(公告)号：US06525394B1
公开(公告)日：2003-02-25
申请号：US09631862
申请日：2000-08-03
申请人： Ray E. Kuhn , David G. Martin , Rose E. Williams
发明人： Ray E. Kuhn , David G. Martin , Rose E. Williams
IPC分类号： H01L2900
CPC分类号： H01L21/761 , H01L21/823878
摘要： The specification describes techniques for isolating noisy subcircuits in integrated analog/digital devices. Isolation is obtained using a modification of triple well isolation wherein the deep isolation implant is restricted to the digital circuits only to prevent noise from the digital circuits from propagating to the analog sections through the buried implant. Resistor sections are also separated from the buried isolation implant.
摘要翻译：该规范描述了用于在集成模拟/数字设备中隔离噪声子电路的技术。使用三重阱隔离的修改获得隔离，其中深度隔离植入物仅限于数字电路，以防止来自数字电路的噪声通过埋入植入物传播到模拟部分。电阻器部分也与埋入式隔离植入物分离。

6. 发明授权

US4188324A Purification of AT-125 失效
标题翻译：纯化AT-125
公开(公告)号：US4188324A
公开(公告)日：1980-02-12
申请号：US960217
申请日：1978-11-13
申请人： David G. Martin
发明人： David G. Martin
IPC分类号： C07D237/32 , C07D261/04
CPC分类号： C07D237/32 , C07D261/04
摘要： Process for the purification of L-(.alpha.s,5s)-.alpha.-amino-3-chloro-4,5-dihydro-5-isoxazoleacetic acid (AT-125). Also provided are AT-125 analogs prepared in the process.
摘要翻译：纯化L-（α，5s）-α-氨基-3-氯-4,5-二氢-5-异恶唑乙酸（AT-125）的方法。还提供了在该过程中制备的AT-125类似物。

7. 发明授权

US06526374B1 Fractional PLL employing a phase-selection feedback counter 失效
标题翻译：采用相位选择反馈计数器的小数PLL
公开(公告)号：US06526374B1
公开(公告)日：2003-02-25
申请号：US09460169
申请日：1999-12-13
申请人： David G. Martin
发明人： David G. Martin
IPC分类号： G06F300
CPC分类号： H03L7/18 , H03L7/0891 , H03L7/0996
摘要： A phase-locked loop (PLL) employs a ring oscillator for the voltage-controlled oscillator (VCO), and the ring oscillator comprises an odd number of inverting stages operating at a given frequency. The frequency of the ring oscillator is determined by the delay through each stage and the number of stages. The output signal of each stage has a phase determined by the number of stages, and each stage provides its output signal with a different phase. The VCO of the PLL selects phases of the ring oscillator to clock the counter of the feedback divider of the PLL. Each phase is selected by a multiplexer (mux) under the control of a finite state machine that monitors the output of the counter. When the counter completes a full count cycle on one phase of the ring oscillator, the finite state machine selects a different phase of the ring oscillator to clock the counter for the next count cycle. The phase selected advances or delays the start of the next count cycle by the delay of one or more stages of the ring oscillator. Thus, for a PLL having a three-stage ring oscillator and a mux selecting the phase from each stage sequentially (first to last) for every count cycle, the effective count of the counter is (V+⅓) or (N−⅓), as opposed to N, depending on whether the selected phase delays or advances the start of the next count cycle.
摘要翻译：锁相环（PLL）使用用于压控振荡器（VCO）的环形振荡器，并且环形振荡器包括以给定频率工作的奇数个反相级。环形振荡器的频率由每个级的延迟和级数决定。每级的输出信号具有由级数确定的相位，并且每个级提供具有不同相位的其输出信号。 PLL的VCO选择环形振荡器的相位来为PLL的反馈分频器的计数器提供时钟。每个相位由多路复用器（多路复用器）选择，在有限状态机的控制下，监视计数器的输出。当计数器在环形振荡器的一个相位上完成一个完整的计数周期时，有限状态机选择环形振荡器的不同相位来计数下一个计数周期。所选择的相位延迟或延迟下一个计数周期的开始由环形振荡器的一个或多个阶段的延迟。因此，对于具有三级环形振荡器和多路复用器的PLL，对于每个计数周期，从每个级顺序地（首先到最后）选择相位，计数器的有效计数为（V + 1/3）或（N- 1/3），与N相反，取决于所选择的相位是延迟还是推进下一个计数周期的开始。

8. 发明授权

US06390193B1 Downhole connector for production tubing and control line and method 有权
标题翻译：生产管道和控制线及方法的井下连接器
公开(公告)号：US06390193B1
公开(公告)日：2002-05-21
申请号：US09713062
申请日：2000-11-15
申请人： David G. Martin , Damien Patton
发明人： David G. Martin , Damien Patton
IPC分类号： E21B4700
CPC分类号： A61B5/0472 , A61B5/04286 , A61N1/3702 , E21B17/06 , E21B23/04 , E21B47/00
摘要： A connector is disclosed to facilitate the testing of a control line or lines adjacent a bottomhole assembly. A running tool is connected to a lower portion of the connector which is, in turn, connected to the bottomhole assembly. The running tool allows testing of the control line adjacent the bottomhole assembly and thereafter, the operation of components of the bottomhole assembly. The running tool is removed and the upper portion of the string, including the mating portion of the connector at its lower end, is inserted into the wellbore. The connector components are self-aligning and lock to each other downhole to complete the production tubing and the control line tubing to the surface. Multiple control lines are envisioned between the surface and the bottomhole assembly. Multiple connectors can be used in a given production string, and provisions can be made for operation of a multiplicity of downhole components from the control line system which extends along the production tubing.
摘要翻译：公开了一种连接器，以便于对靠近井底组件的控制线或线的测试。运行工具连接到连接器的下部，该下部又连接到井底组件。运行工具允许对靠近井下组件的控制线进行测试，然后测试井底组件的部件的操作。移除运行工具，并且包括其下端处的连接器的配合部分的绳的上部插入到井筒中。连接器部件是自对准的并且彼此锁定在井下，以将生产管道和控制管线完成到表面。在表面和井底组件之间设想了多条控制线。可以在给定的生产线中使用多个连接器，并且可以对沿着生产管道延伸的控制线系统的多个井下部件进行操作。

9. 发明授权

US06389553B1 Redundant link delay maintenance circuit and method 失效
标题翻译：冗余链路延时维护电路及方法
公开(公告)号：US06389553B1
公开(公告)日：2002-05-14
申请号：US09083999
申请日：1998-05-26
申请人： David William Denike , David G. Martin
发明人： David William Denike , David G. Martin
IPC分类号： H04L122
CPC分类号： H04L1/22 , H04L7/005
摘要： A system and method for maintaining a constant delay when a switch between two or more possible input data streams is made. Data received on a selected stream is buffered as it is received, the timing of this buffering being based on link timing recovered from the selected stream. Stable local timing information is generated from the link timing. It is stable in the sense that it is subject to only a very small shift when a switch in the selected data stream is made. Data is then read from the buffer on the basis of the local timing information thereby producing an output stream with a constant delay.
摘要翻译：当在两个或多个可能的输入数据流之间进行切换时，用于维持恒定延迟的系统和方法。在所选流上接收到的数据在接收时被缓冲，这种缓冲的定时是基于从所选择的流中恢复的链路定时。从链路定时产生稳定的本地定时信息。在所选择的数据流中的切换被做成时，它是稳定的。然后基于本地定时信息从缓冲器读取数据，从而产生具有恒定延迟的输出流。

10. 发明授权

US6107829A Low leakage tristatable MOS output driver 失效
标题翻译：低泄漏三态MOS输出驱动器
公开(公告)号：US6107829A
公开(公告)日：2000-08-22
申请号：US52074
申请日：1998-03-31
申请人： David G. Martin
发明人： David G. Martin
IPC分类号： H03K19/003 , H03K19/00 , H03K19/0175 , H03K19/02 , H03K19/094
CPC分类号： H03K19/00315
摘要： In accordance with the present invention there is provided a tristatable digital MOS output buffer/driver having a significantly reduced subthreshold leakage current. The buffer of the present invention comprises three P-channel transistor devices and three N-channel transistor devices. A reduced subthreshold leakage current is achieved by having the source of the output N-channel transistor device and the output P-channel transistor device connected to nodes having a variable voltage. This adjusts the source-to-body voltages of the output N-channel and P-channel transistor devices to be equal in magnitude to the voltage of the positive supply, resulting in the reduction of subthreshold leakage currents.
摘要翻译：根据本发明，提供了具有明显减小的亚阈值漏电流的可跟踪数字MOS输出缓冲器/驱动器。本发明的缓冲器包括三个P沟道晶体管器件和三个N沟道晶体管器件。通过使输出N沟道晶体管器件的源极和输出P沟道晶体管器件连接到具有可变电压的节点来实现减小的亚阈值漏电流。这将调节输出N沟道和P沟道晶体管器件的源极到体电压的幅度与正电源的电压相等，导致亚阈值漏电流的减小。

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