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1. 发明申请

US20130347084A1 Security Mode for Mobile Communications Devices 有权
标题翻译：移动通信设备的安全模式
公开(公告)号：US20130347084A1
公开(公告)日：2013-12-26
申请号：US13528345
申请日：2012-06-20
申请人： Richard Malinowski
发明人： Richard Malinowski
IPC分类号： H04W12/08
CPC分类号： G06F21/50 , G06F21/31 , G06F21/629 , G06F21/74 , G06F2221/2105 , G06F2221/2141 , H04L63/08 , H04L63/107 , H04L63/123 , H04M1/7253 , H04M1/72577 , H04M2250/10 , H04N21/41407 , H04N21/4334 , H04N21/4524 , H04N21/4627 , H04W4/50 , H04W12/08 , H04W12/10 , H04W84/08 , H04W88/06
摘要： A system and method of implementing a security mode in a mobile communications device, including a mobile communications device comprising a processor, and a computer readable storage medium storing programming for execution by the processor, the programming including instructions to activate a security mode of the mobile communications device, and pursuant to activation of the security mode, disable a first class of features of the mobile communications device, wherein other features of the mobile communications device remain enabled after activation of the mobile security.
摘要翻译：一种在移动通信设备中实现安全模式的系统和方法，包括包括处理器的移动通信设备和存储用于由处理器执行的程序的计算机可读存储介质，该程序包括激活移动设备的安全模式的指令通信设备，并且根据安全模式的激活，禁用移动通信设备的第一类特征，其中移动通信设备的其他特征在激活移动安全性之后保持启用。

2. 发明授权

US08756669B2 Security mode for mobile communications devices 有权
标题翻译：移动通信设备的安全模式
公开(公告)号：US08756669B2
公开(公告)日：2014-06-17
申请号：US13528345
申请日：2012-06-20
申请人： Richard Malinowski
发明人： Richard Malinowski
IPC分类号： H04W12/08 , G06F21/50 , H04W12/10 , G06F21/31 , H04L29/06 , H04W84/08
CPC分类号： G06F21/50 , G06F21/31 , G06F21/629 , G06F21/74 , G06F2221/2105 , G06F2221/2141 , H04L63/08 , H04L63/107 , H04L63/123 , H04M1/7253 , H04M1/72577 , H04M2250/10 , H04N21/41407 , H04N21/4334 , H04N21/4524 , H04N21/4627 , H04W4/50 , H04W12/08 , H04W12/10 , H04W84/08 , H04W88/06
摘要： A system and method of implementing a security mode in a mobile communications device, including a mobile communications device comprising a processor, and a computer readable storage medium storing programming for execution by the processor, the programming including instructions to activate a security mode of the mobile communications device, and pursuant to activation of the security mode, disable a first class of features of the mobile communications device, wherein other features of the mobile communications device remain enabled after activation of the mobile security.
摘要翻译：一种在移动通信设备中实现安全模式的系统和方法，包括包括处理器的移动通信设备和存储用于由处理器执行的程序的计算机可读存储介质，该程序包括激活移动设备的安全模式的指令通信设备，并且根据安全模式的激活，禁用移动通信设备的第一类特征，其中移动通信设备的其他特征在激活移动安全性之后保持启用。

3. 发明授权

US5603010A Performing speculative system memory reads prior to decoding device code 失效
标题翻译：在解码设备代码之前执行推测系统存储器读取
公开(公告)号：US5603010A
公开(公告)日：1997-02-11
申请号：US580323
申请日：1995-12-28
申请人： James M. Dodd , Richard Malinowski , Brian K. Langendorf , George R. Hayek
发明人： James M. Dodd , Richard Malinowski , Brian K. Langendorf , George R. Hayek
IPC分类号： G06F12/04 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4239
摘要： A method of improving computer system performance during memory reads. Prior art computer systems experience a considerable time penalty during microprocessor reads from system memory. This time penalty is mitigated by the method of the present invention, wherein data is speculatively retrieved from system memory upon receipt of a microprocessor read request. A microprocessor initiates a read request which is decoded by a memory controller. Before the decoding has completed, the memory controller speculatively begins to retrieve data from the system memory device. Thus if the decode step determines that the requested data is in system memory, the time required to retrieve the data is decreased.
摘要翻译：一种在存储器读取期间提高计算机系统性能的方法。现有技术的计算机系统在从系统存储器的微处理器读取期间经历相当多的时间损失。通过本发明的方法减轻了该时间的损失，其中在接收到微处理器读取请求时，从系统存储器中推测性地检索数据。微处理器启动由存储器控制器解码的读请求。在解码完成之前，存储器控制器推测开始从系统存储器件中检索数据。因此，如果解码步骤确定所请求的数据在系统存储器中，则检索数据所需的时间减少。

4. 发明授权

US5553023A Memory partitioning 失效
标题翻译：内存分区
公开(公告)号：US5553023A
公开(公告)日：1996-09-03
申请号：US421321
申请日：1995-04-13
申请人： Winnie K. W. Lau , Richard Malinowski
发明人： Winnie K. W. Lau , Richard Malinowski
IPC分类号： G06F12/12 , G11C8/12 , G11C29/00 , G11C13/00
CPC分类号： G11C29/88 , G06F12/125 , G11C8/12 , G06F12/126
摘要： This invention relates to an improved memory storage system which allows selective ranges of memory locations, which can also be referred to as virtual memory banks, to be enabled and disabled. The ranges of memory locations can be disabled to avoid refreshing unused memory location and to eliminate faulty memory locations. Also, the ranges of memory locations can be treated as blocks or banks of memory regardless of the physical chips used to store the data. In other words, if a memory bank has a capacity of 16 MB, the range of memory locations may be a portion of the total capacity of this memory bank, for example 8 MB or 4 MB, and the remainder of the memory bank can be unaffected or be the subject of another range of memory locations. In a preferred embodiment, the ranges of memory locations is at least 2 MB in size.
摘要翻译：本发明涉及一种改进的存储器存储系统，其允许选择性地存储位置（也可以称为虚拟存储体）被启用和禁用。可以禁用存储器位置的范围，以避免刷新未使用的存储器位置并消除故障存储器位置。而且，无论用于存储数据的物理芯片如何，存储器位置的范围可被视为存储器块或存储体。换句话说，如果存储体具有16MB的容量，则存储器位置的范围可以是该存储体的总容量的一部分，例如8MB或4MB，并且存储体的其余部分可以是不受影响或成为另一范围记忆位置的主题。在优选实施例中，存储器位置的范围大小至少为2MB。

5. 发明授权

US4918353A Reflector and lamp combination 失效
标题翻译：反射器和灯组合
公开(公告)号：US4918353A
公开(公告)日：1990-04-17
申请号：US366336
申请日：1989-06-13
申请人： Clark D. Nelson , Richard Malinowski , Catherine Mers , Diana Essock , Vito Arsena , Mary Jaffe
发明人： Clark D. Nelson , Richard Malinowski , Catherine Mers , Diana Essock , Vito Arsena , Mary Jaffe
IPC分类号： C04B12/02 , C04B28/34 , F21V19/00 , H01J5/58
CPC分类号： H01J5/58 , C04B12/022 , C04B28/34 , F21V19/0005 , C04B2111/00844 , Y02W30/92
摘要： This invention relates to a glass reflector and tungsten-halogen lamp combination wherein the lamp is cemented into the glass reflector with an aluminum phosphate cement composition which comprise a mixture of aluminum phosphate containing excess phosphoric acid, relatively small particle size alumina and a mixture of relatively medium and coarse particle size inert filler materials and wherein the lamp contains a hermetic seal between quartz and a molybdenum foil with that portion of the foil in the seal area which is exposed to an oxidizing environment coated with alkali metal silicate.
摘要翻译：本发明涉及一种玻璃反射器和卤钨灯组合，其中灯用磷酸铝水泥组合物胶合到玻璃反射器中，磷酸铝水泥组合物包含含有过量磷酸的磷酸铝的混合物，相对较小粒径的氧化铝和相对较小的粒度的氧化铝中等和粗粒度的惰性填料，其中该灯在石英和钼箔之间包含密封区域中的该箔部分的气密密封，所述密封区域暴露于用碱金属硅酸盐涂覆的氧化环境。

6. 发明授权

US06148380A Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus 失效
标题翻译：用于控制同步DRAM型存储器和系统总线之间的数据传输的方法和装置
公开(公告)号：US06148380A
公开(公告)日：2000-11-14
申请号：US735433
申请日：1997-01-02
申请人： James M. Dodd , Richard Malinowski
发明人： James M. Dodd , Richard Malinowski
IPC分类号： G06F13/16 , G06F13/00
CPC分类号： G06F13/1631
摘要： An interface and method for a synchronous DRAM (syncDRAM) memory are provided that improve performance. The read operation in a syncDRAM is significantly sped up by eliminating the step of opening a new page of data in a SyncDRAM using a speculative read method. This provides the ability to open a page of information in the SyncDRAM with a command generator in response to a data request. Speculative read logic is also included to continue reading from the page with an invalid address until a second read request occurs. Thus, in the event that a subsequent read request occurs that requests data located on the same page as the prior request, the data can be indexed and read from a location on that page without having to first assert the SCS# and SCAS#. This frequently removes the step of opening a page from the read process and, over time, can significantly speed up the overall SyncDRAM reads in a computer system.
摘要翻译：提供了用于提高性能的同步DRAM（syncDRAM）存储器的接口和方法。通过消除使用推测读取方法在SyncDRAM中打开新页面的数据的步骤，syncDRAM中的读取操作显着加快。这提供了使用命令生成器在SyncDRAM中打开一页信息以响应数据请求的能力。还包括推测读取逻辑，以继续从具有无效地址的页面读取，直到发生第二个读取请求。因此，在发生请求与先前请求相同的页面上的数据的后续读取请求的情况下，可以从该页面上的位置索引和读取数据，而无需首先断言SCS＃和SCAS＃。这经常删除从读取过程打开页面的步骤，并且随着时间的推移，可以显着加快计算机系统中的整体SyncDRAM读取速度。

7. 发明授权

US06044441A Method and apparatus for encoding valid and invalid states in a cache with an invalid pattern 失效
标题翻译：用于在无效模式的高速缓存中对有效和无效状态进行编码的方法和装置
公开(公告)号：US06044441A
公开(公告)日：2000-03-28
申请号：US979276
申请日：1997-11-26
申请人： Richard Malinowski
发明人： Richard Malinowski
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0802 , G06F12/0891
摘要： A cache controller unit includes an address comparator unit for comparing an address to be accessed in memory with a tag address. An invalid pattern comparator is coupled to the address comparator. The invalid pattern comparator operates to compare the tag address with an invalid pattern. A qualifier unit is coupled to the address comparator and the invalid pattern comparator. The qualifier unit outputs a signal when the address to be accessed in the memory matches the tag address in the address tag and the address tag does not match the invalid pattern.
摘要翻译：高速缓存控制器单元包括用于将存储器中要访问的地址与标签地址进行比较的地址比较器单元。无效模式比较器耦合到地址比较器。无效模式比较器用于比较标签地址与无效模式。限定单元耦合到地址比较器和无效模式比较器。当存储器中要访问的地址与地址标签中的标签地址匹配并且地址标签与无效模式不匹配时，限定单元输出信号。

8. 发明授权

US6000017A Hybrid tag architecture for a cache memory 失效
标题翻译：用于缓存的混合标签体系结构
公开(公告)号：US6000017A
公开(公告)日：1999-12-07
申请号：US909347
申请日：1997-08-11
申请人： George Hayek , Richard Malinowski
发明人： George Hayek , Richard Malinowski
IPC分类号： G06F12/08
CPC分类号： G06F12/0893 , G06F12/0804
摘要： A cache memory system having a hybrid tag architecture and a series of data lines is disclosed. The cache memory includes a cache controller and a dirty tag memory included within the cache controller. The dirty tag memory indicates the status of each data line in the cache memory. A tag memory is coupled to the cache controller and is located external to the cache controller.
摘要翻译：公开了具有混合标签架构和一系列数据线的高速缓冲存储器系统。高速缓冲存储器包括缓存控制器和包含在高速缓存控制器内的脏标签存储器。脏标记存储器指示高速缓冲存储器中每条数据线的状态。标签存储器耦合到高速缓存控制器并且位于高速缓存控制器的外部。

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