会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Detecting servo data and servo bursts from discrete time samples of an
analog read signal in a sampled amplitude read channel
    • 在采样振幅读通道中从模拟读信号的离散时间采样中检测伺服数据和伺服脉冲串
    • US5668678A
    • 1997-09-16
    • US325842
    • 1994-11-14
    • David E. ReedRichard T. BehernsWilliam G. Bliss
    • David E. ReedRichard T. BehernsWilliam G. Bliss
    • G11B5/596G11B21/08G11B21/10G11B5/09
    • G11B21/083G11B21/085G11B21/106G11B5/59655G11B5/59688G11B20/10037G11B20/10055
    • A discrete time servo demodulation technique incorporated within a sampled amplitude read channel to demodulate embedded servo field information stored on a magnetic medium. The servo field information is transduced by a read head into an analog signal, and converted to a sequence of sample values in the read channel. The demodulation technique is responsive to the sample values and includes a discrete time peak detector for detecting servo data, and a discrete time servo burst amplitude detector for measuring the amplitude of servo bursts. Peaks are detected in the analog read signal by sensing a change of slope from the sequence of sample values. The peaks are qualified by polarity in that a peak is detected only if its polarity is opposite in sign from the previous peak. The servo burst amplitudes are measured by interpolating, rectifying, and accumulating the sequence of sample values corresponding to the servo bursts. A plurality of registers store the amplitude measurement of corresponding servo bursts such as the four servo bursts in a quadrature system. The sample values are interpolated, squared, and the sampling frequency dithered in order to decrease the sensitivity of the burst amplitude measurement to variations in the sampling phase and to increase the effective resolution of the read channel ADC for servo demodulation. Control signals are generated in response to the detected servo data which are transferred to a servo controller over a fully digital interface, thus obviating the analog-to-digital converter found in conventional servo controllers.
    • 一种并入采样振幅读通道内的离散时间伺服解调技术,用于解调存储在磁介质上的嵌入式伺服场信息。 伺服字段信息由读取头转换为模拟信号,并转换为读通道中的一系列采样值。 解调技术响应于采样值,并且包括用于检测伺服数据的离散时间峰值检测器和用于测量伺服脉冲串幅度的离散时间伺服脉冲串幅度检测器。 通过从样本值序列感测斜率的变化,在模拟读取信号中检测峰。 峰由极性限定,只有当峰的极性与前一峰的符号相反时才检测到峰。 通过内插,整流和累加对应于伺服脉冲串的采样值序列来测量伺服脉冲串幅度。 多个寄存器将相应伺服脉冲串的振幅测量值存储在正交系统中,例如四个伺服脉冲串。 样本值被内插,平方,并且采样频率抖动,以便将脉冲串幅度测量的灵敏度降低到采样相位的变化并且增加用于伺服解调的读通道ADC的有效分辨率。 响应于通过全数字接口传送到伺服控制器的检测到的伺服数据产生控制信号,从而避免了在常规伺服控制器中发现的模拟 - 数字转换器。
    • 3. 发明授权
    • Sampled amplitude read channel employing early-decisions from a trellis sequence detector for sampling value estimation
    • 采样幅度读取信道采用来自网格序列检测器的早期判决来进行采样值估计
    • US06246723B1
    • 2001-06-12
    • US09072285
    • 1998-05-04
    • William G. BlissDavid E. ReedMarvin L. VisGerman S. Feyh
    • William G. BlissDavid E. ReedMarvin L. VisGerman S. Feyh
    • H04L512
    • G11B20/10009G11B20/10055H03M13/3961H03M13/41H03M13/6331H03M13/6343H04L1/0054
    • A sampled amplitude read channel is disclosed for disc storage systems that extracts early-decisions from a discrete-time trellis sequence detector to generate estimated target values for use in decision-directed timing recovery, gain control, and adaptive equalization. The trellis sequence detector comprises a metric generator for generating error metrics corresponding to a plurality of states of a state transition diagram, and a plurality of path memories which correspond to the paths of a trellis. The path memories store a plurality of survivor sequences which eventually merge into a most likely sequence at the output of the path memories. To reduce the latency in generating the estimated target samples, the trellis sequence detector outputs an early-decision from an intermediate location within the path memories. The early-decision is then converted into the partial response signaling space of the read signal samples. To improve the accuracy in estimating the target sample values, the accumulated metrics of a predetermined number of states are compared and the early-decision value is selected from the path memory having the smallest error metric. Alternatively, a majority-vote circuit evaluates the intermediate values stored in a predetermined number of the path memories and outputs the intermediate value that occurs most frequently. Although the early-decision technique of the present invention requires more latency than a simple slicer circuit, during acquisition the estimated target sample values are not used and therefore the increase in latency is not a significant problem.
    • 公开了用于从离散时间网格序列检测器提取早期决定以产生用于决策定时恢复,增益控制和自适应均衡的估计目标值的盘存储系统的采样幅度读取信道。 网格序列检测器包括用于产生与状态转移图的多个状态相对应的误差度量的度量发生器,以及对应于网格的路径的多个路径存储器。 路径存储器存储多个幸存者序列,其最终在路径存储器的输出处合并成最可能的序列。 为了减少生成估计的目标样本的延迟,网格序列检测器从路径存储器内的中间位置输出早期决定。 然后将早期决定转换为读取信号样本的部分响应信令空间。 为了提高估计目标采样值的准确性,比较预定数量状态的累积度量,并从具有最小误差度量的路径存储器中选择早期判定值。 或者,多数投票电路评估存储在预定数量的路径存储器中的中间值,并输出最频繁出现的中间值。 虽然本发明的早期决策技术比简单的限幅器电路需要更多的延迟,但在采集期间,不使用估计的目标采样值,因此等待时间的增加不是一个显着的问题。
    • 4. 发明授权
    • Fault tolerant sync mark detector for synchronizing a time varying
sequence detector in a sampled amplitude read channel
    • 容错同步标记检测器,用于使采样幅度读通道中的时变序列检测器同步
    • US6023386A
    • 2000-02-08
    • US961727
    • 1997-10-31
    • David E. ReedWilliam G. Bliss
    • David E. ReedWilliam G. Bliss
    • G11B5/09G11B20/10G11B20/14G11B27/30
    • G11B20/10055G11B20/10037G11B20/1403G11B27/3027G11B5/09G11B20/10009
    • In a magnetic disk storage system, a sampled amplitude read channel is disclosed that employs a fault tolerant sync mark detector for detecting a sync mark from the channel samples in order to synchronize a time varying sequence detector. The read channel preferably employs PR4 equalization for timing recovery and gain control, and EEPR4 equalization for sequence detection. The EEPR4 sequence detector operates according to a time varying state machine matched to a predetermined trellis code constraint. Because the state machine is time varying, the data stream must be synchronized at the input of the sequence detector rather than at the output as in the prior art. The present invention provides a fault tolerant sync mark detector that detects a sync mark from the EEPR4 channel samples before being input into the sequence detector. In one embodiment, the sync mark detector accumulates a squared error between the read signal sample values and the target sample values of the target sync mark; the sync mark is detected when the accumulated squared error is less than a predetermined lower threshold. In an alternative embodiment, the sync mark detector computes a correlation between the read signal sample values and the target sample values of the target sync mark; the sync mark is detected when the correlation is greater than a predetermined upper threshold. The correlation sync mark detector is the preferred embodiment because it is insensitive to d.c. offsets, it exhibits excellent performance in detecting short sync marks, and it can be implemented as two cascaded finite impulse response filters without requiring multipliers or squarers.
    • 在磁盘存储系统中,公开了一种采样幅度读取通道,其采用容错同步标记检测器来检测来自信道样本的同步标记,以便使时变序列检测器同步。 读通道优选采用PR4均衡来进行定时恢复和增益控制,以及用于序列检测的EEPR4均衡。 EEPR4序列检测器根据与预定网格码约束匹配的时变状态机进行操作。 因为状态机是时变的,所以在现有技术中数据流必须在序列检测器的输入端而不是在输出端被同步。 本发明提供一种容错同步标记检测器,其在输入到序列检测器之前,从EEPR4信道样本中检测同步标记。 在一个实施例中,同步标记检测器在读取信号采样值和目标同步标记的目标采样值之间累积平方误差; 当累积的平方误差小于预定的下限阈值时,检测同步标记。 在替代实施例中,同步标记检测器计算读取信号采样值和目标同步标记的目标采样值之间的相关性; 当相关性大于预定的上限阈值时,检测同步标记。 相关同步标记检测器是优选实施例,因为它对直流不敏感。 它在检测短同步标记方面具有出色的性能,并且可以实现为两个级联有限脉冲响应滤波器,而不需要乘法器或平方器。
    • 5. 发明授权
    • Sampled amplitude read channel employing interpolated timing recovery
and a remod/demod sequence detector
    • 采用内插定时恢复的采样幅度读取通道和重构/解调序列检测器
    • US5771127A
    • 1998-06-23
    • US681678
    • 1996-07-29
    • David E. ReedWilliam R. Foland, Jr.William G. BlissRichard T. BehrensLisa C. Sundell
    • David E. ReedWilliam R. Foland, Jr.William G. BlissRichard T. BehrensLisa C. Sundell
    • G11B20/10G11B20/14G11B5/09
    • G11B20/10055G11B20/10009G11B20/10037G11B20/1426
    • In a computer disk storage system for recording binary data, a sampled amplitude read channel comprises a sampling device for asynchronously sampling pulses in an analog read signal from a read head positioned over a disk storage medium, interpolated timing recovery for generating synchronous sample values, and a sequence detector for detecting the binary data from the synchronous sample values. The sequence detector comprises a demodulator for detecting a preliminary binary sequence which may contain bit errors, a remodulator for remodulating to estimated sample values, a means for generating sample error values, an error pattern detector for detecting the bit errors, an error detection validator, and an error corrector for correcting the bit errors. The remodulator comprises a partial erasure circuit which compensates for the non-linear reduction in amplitude of a primary pulse caused by secondary pulses located near the primary pulse. The error pattern detector comprises a peak error pattern detector and, if an error pattern is detected, a means for disabling the error pattern detector until the detected error pattern has been fully processed. The error detection validator checks the validity of a detected error event and, if valid, enables operation of the error corrector.
    • 在用于记录二进制数据的计算机磁盘存储系统中,采样幅度读取通道包括用于从位于盘存储介质上的读取头的模拟读取信号中异步采样脉冲的采样装置,用于产生同步采样值的内插定时恢复,以及 序列检测器,用于从同步样本值检测二进制数据。 序列检测器包括用于检测可能包含位错误的初步二进制序列的解调器,用于重新调制到估计样本值的再调制器,用于产生采样误差值的装置,用于检测位错误的误差模式检测器,错误检测验证器, 以及用于校正位错误的纠错器。 再调制器包括部分擦除电路,其补偿由位于主脉冲附近的次级脉冲引起的初级脉冲的幅度的非线性减小。 误差模式检测器包括峰值误差模式检测器,并且如果检测到错误模式,则用于禁止错误模式检测器的装置,直到检测到的错误模式被完全处理为止。 错误检测验证器检查检测到的错误事件的有效性,如果有效,则允许错误校正器的操作。
    • 6. 发明授权
    • Detecting servo data and servo bursts from discrete time samples of an
analog read signal in a sampled amplitude read channel
    • 在采样振幅读通道中从模拟读信号的离散时间采样中检测伺服数据和伺服脉冲串
    • US6144513A
    • 2000-11-07
    • US166598
    • 1998-09-28
    • David E. ReedWilliam G. BlissRichard T. Behems
    • David E. ReedWilliam G. BlissRichard T. Behems
    • G11B5/596G11B21/08G11B21/10G11B5/09G11B5/02
    • G11B21/083G11B21/085G11B21/106G11B5/59655G11B5/59688G11B20/10037G11B20/10055
    • A discrete time servo demodulation technique incorporated within a sampled amplitude read channel to demodulate embedded servo field information stored on a magnetic medium. The servo field information is transduced by a read head into an analog signal, and converted to a sequence of sample values in the read channel. The demodulation technique is responsive to the sample values and includes a discrete time peak detector for detecting servo data, and a discrete time servo burst amplitude detector for measuring the amplitude of servo bursts. Peaks are detected in the analog read signal by sensing a change of slope from the sequence of sample values. The peaks are qualified by polarity in that a peak is detected only if its polarity is opposite in sign from the previous peak. The servo burst amplitudes are measured by interpolating, rectifying, and accumulating the sequence of sample values corresponding to the servo bursts. A plurality of registers store the amplitude measurement of corresponding servo bursts such as the four servo bursts in a quadrature system. The sample values are interpolated, squared, and the sampling frequency dithered in order to decrease the sensitivity of the burst amplitude measurement to variations in the sampling phase and to increase the effective resolution of the read channel ADC for servo demodulation. Control signals are generated in response to the detected servo data which are transferred to a servo controller over a fully digital interface, thus obviating the analog-to-digital converter found in conventional servo controllers.
    • 一种并入采样振幅读通道内的离散时间伺服解调技术,用于解调存储在磁介质上的嵌入式伺服场信息。 伺服字段信息由读取头转换为模拟信号,并转换为读通道中的一系列采样值。 解调技术响应于采样值,并且包括用于检测伺服数据的离散时间峰值检测器和用于测量伺服脉冲串幅度的离散时间伺服脉冲串幅度检测器。 通过从样本值序列感测斜率的变化,在模拟读取信号中检测峰。 峰由极性限定,只有当峰的极性与前一峰的符号相反时才检测到峰。 通过内插,整流和累加对应于伺服脉冲串的采样值序列来测量伺服脉冲串幅度。 多个寄存器将相应伺服脉冲串的振幅测量值存储在正交系统中,例如四个伺服脉冲串。 样本值被内插,平方,并且采样频率抖动,以便将脉冲串幅度测量的灵敏度降低到采样相位的变化并且增加用于伺服解调的读通道ADC的有效分辨率。 响应于通过全数字接口传送到伺服控制器的检测到的伺服数据产生控制信号,从而避免了在常规伺服控制器中发现的模拟 - 数字转换器。
    • 7. 发明授权
    • PR4 sampled amplitude read channel for detecting user data and embedded
servo data
    • PR4采样幅度读通道,用于检测用户数据和嵌入式伺服数据
    • US06115198A
    • 2000-09-05
    • US960471
    • 1997-10-29
    • David E. ReedWilliam G. Bliss
    • David E. ReedWilliam G. Bliss
    • G11B5/09
    • G11B5/5965G11B20/10074G11B20/10175G11B20/10277G11B2020/10916G11B2020/1267G11B2020/1281G11B2220/2516
    • A partial response class-IV (PR4) sampled amplitude read channel is disclosed for detecting user data and embedded servo data. The detected servo data is encoded using a novel servo code capable of accurately decoding detected codewords representing servo track address during seek operations, even when the recording head flies between two adjacent tracks, and capable of correcting errors in the detected codedwords caused by noise in the read signal, such as inter-symbol interference. In one embodiment, the servo code corrects certain minimum distance error events, such as a bit shift error event, associated with a trellis type sequence detector. To achieve the equivalent effect of a conventional Gray code, the codewords are arranged such that adjacent track addresses differ by a number of bits relative to the minimum distance error events corrected. In this manner, when the recording head spans two adjacent tracks during a seek operation, the ambiguity in the detected codeword will be resolved in favor of one of the adjacent track addresses. To further increase performance, the servo data PR4 sample values are converted into an EPR4 response and detected with a sliding threshold detector. This modification provides the same performance gain as a PR4 sequence detector matched to a d=1 constraint, but at less cost. One of the PR4 sliding threshold detectors for detecting user data can be advantageously shared to detect the servo data-the only additional hardware required is a 1+D filter for converting the PR4 samples of the servo data to EPR4 samples.
    • 公开了用于检测用户数据和嵌入式伺服数据的部分响应类别IV(PR4)采样幅度读取信道。 检测到的伺服数据使用能够在搜索操作期间精确地解码表示伺服磁道地址的检测码字的新型伺服码进行编码,即使当记录头在两个相邻轨道之间飞行时,也能够校正由于噪声引起的检测到的编码字中的错误 读信号,如符号间干扰。 在一个实施例中,伺服代码校正与网格类型序列检测器相关联的某些最小距离误差事件,例如位移错误事件。 为了实现常规格雷码的等效效果,码字被布置成使得相邻的轨道地址相对于校正的最小距离误差事件相差多个位。 以这种方式,当在搜索操作期间记录头跨越两个相邻轨道时,检测到的码字中的模糊度将被解析为有利于相邻轨道地址之一。 为了进一步提高性能,伺服数据PR4采样值被转换成EPR4响应并用滑动阈值检测器检测。 该修改提供与与d = 1约束匹配的PR4序列检测器相同的性能增益,但是以较低的成本。 用于检测用户数据的PR4滑动阈值检测器之一可以有利地被共享以检测伺服数据 - 所需的唯一附加硬件是用于将伺服数据的PR4采样转换为EPR4样本的1 + D滤波器。
    • 9. 发明授权
    • Parity channel code for enhancing the operation of a remod/demod
sequence detector in a d=1 sampled amplitude read channel
    • 奇偶信道码,用于增强d = 1采样幅度读信道中的重索/解调序列检测器的操作
    • US6052248A
    • 2000-04-18
    • US16004
    • 1998-01-30
    • David E. ReedWilliam G. Bliss
    • David E. ReedWilliam G. Bliss
    • G11B20/10G11B5/09
    • G11B20/1403G11B20/10009G11B20/10037G11B20/10055G11B20/10064
    • A sampled amplitude read channel is disclosed for disk storage systems employing a run-length limited (RLL) d=1 channel code which compensates for partial erasure, and a parity channel code for enhancing the operation of a remod/demod sequence detector. During a write operation, after encoding the user data into codewords comprising the RLL d=1 constraint, the parity over one interleave of a block of NRZI bits is computed and two parity bits appended to form a parity codeword. For an even number of "1" bits in the block, the parity bits are set to "00". For an odd number of "1" bits in the block, the parity bits are set to "10" if the codeword ends with a "0" bit and to "01" if the codeword ends with a "1" bit, thereby maintaining the RLL d=1 constraint. Thus, a parity codeword will always comprise an even number of "1" bits (even parity). During read back, a parity syndrome is generated over a detected parity codeword; if the parity syndrome indicates the codeword comprises an odd number of "1" bits (odd parity), then the codeword is corrected according to the most likely error made by the remod/demod sequence detector. As a result, the remod/demod sequence detector of the present invention approaches the distance enhanced performance of matching a trellis state machine to the parity constraint, but with significantly less circuitry.
    • 对采用补偿部分擦除的游程限制(RLL)d = 1信道码的磁盘存储系统和用于增强重构/解调序列检测器的操作的奇偶校验信道码,公开了采样幅度读取信道。 在写操作期间,在将用户数据编码成包括RLL d = 1约束的码字之后,计算NRZI比特块的一个交织上的奇偶校验,并且附加两个奇偶校验位以形成奇偶码字。 对于块中的偶数“1”位,奇偶校验位设置为“00”。 对于块中的奇数“1”位,如果代码字以“1”位结束,则如果码字以“0”位结束,则奇偶校验位被设置为“10”,从而保持 RLL d = 1约束。 因此,奇偶码字将总是包括偶数“1”比特(偶校验)。 在回读期间,在检测到的奇偶码字上产生奇偶校验; 如果奇偶校验子码表示码字包括奇数“1”比特(奇校验),则根据由重构/解调序列检测器做出的最可能的错误来校正码字。 结果,本发明的重构/解调序列检测器接近将网格状态机匹配到奇偶校验约束的距离增强性能,但是具有显着更少的电路。
    • 10. 发明授权
    • Adaptive equalization in a sub-sampled read channel for a disk storage
system
    • 用于磁盘存储系统的子采样读通道中的自适应均衡
    • US5966415A
    • 1999-10-12
    • US876054
    • 1997-06-13
    • William G. BlissSian SheDavid E. Reed
    • William G. BlissSian SheDavid E. Reed
    • G11B20/10G11B20/14H04L25/03H04B1/10
    • G11B20/10055G11B20/10009G11B20/10037G11B20/1403H04L2025/03369H04L2025/03471H04L2025/03617
    • A sampled amplitude read channel for disk storage systems is disclosed which asynchronously sub-samples an analog read signal significantly below the Nyquist rate (the baud rate) in order to increase the effective data rate without increasing the frequency of the sampling device. Interpolated timing recovery up-samples the asynchronous samples to generate sample values synchronized to the baud rate, and a Viterbi sequence detector detects the recorded digital data from the synchronous sample values. To compensate for the time-varying characteristics of the recording device, a discrete-time equalizer adaptively equalizes the asynchronous sample values using a least mean square (LMS) adaptive algorithm,W.sub.k+1 =W.sub.k -.mu..multidot.e.sub.k .multidot.X.sub.k,where W.sub.k is a vector of FIR filter coefficients, .mu. is a programmable gain, e.sub.k is a sample error between the FIR filter's actual output and a desired output, and X.sub.k is a vector of samples values from the FIR filter input.
    • 公开了用于磁盘存储系统的采样幅度读取通道,其异步地对模拟读取信号进行子采样,显着低于奈奎斯特速率(波特率),以增加有效数据速率而不增加采样设备的频率。 内插定时恢复对异步采样进行上采样,以生成与波特率同步的采样值,维特比序列检测器根据同步采样值检测记录的数字数据。 为了补偿记录装置的时变特性,离散时间均衡器使用最小均方(LMS)自适应算法自适应地均衡异步采样值,即+ E,uns W + EE k + 1 = + E,uns W + EE k-mu xekx + E,uns X + EE k,其中+ E,uns W + EE k是FIR滤波器系数的向量,mu是可编程增益,ek是FIR滤波器的实际输出之间的采样误差 和期望输出,+ E,uns X + EE k是来自FIR滤波器输入的采样值的向量。