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1. 发明授权

US5617283A Self-referencing modulation circuit for CMOS integrated circuit electrostatic discharge protection clamps 失效
标题翻译：用于CMOS集成电路静电放电保护钳的自参考调制电路
公开(公告)号：US5617283A
公开(公告)日：1997-04-01
申请号：US697124
申请日：1996-08-20
申请人： David B. Krakauer , Kaizad Mistry , Steven Butler , Hamid Partovi
发明人： David B. Krakauer , Kaizad Mistry , Steven Butler , Hamid Partovi
IPC分类号： H02H3/00 , H02H9/04
CPC分类号： H02H9/046 , H02H3/006
摘要： An ESD protection device is provided which includes a self referencing modulation circuit for controlling its operation. The modulation circuit includes a diode stack coupled to a resistor and further coupled to an inverter powered by the signal pad voltage in one embodiment, or an odd plurality of series connected inverters powered by the signal pad voltage in an alternate embodiment. The inverter chain is coupled to the ESD clamp. The modulation circuit requires no reference supply voltage to operate. The ESD protection circuit shunts currents associated with ESD events away from ICs as well as clamping I/O pad voltages to acceptable levels during an ESD event.
摘要翻译：提供一种ESD保护装置，其包括用于控制其操作的自参考调制电路。调制电路包括耦合到电阻器的二极管堆叠，并且还在一个实施例中耦合到由信号焊盘电压供电的逆变器，或者在替代实施例中由信号焊盘电压供电的奇数多个串联连接的逆变器。逆变器链耦合到ESD钳位。调制电路不需要参考电源电压工作。 ESD保护电路将与ESD相关的电流与IC相连，并将I / O焊盘电压钳制到可接受的ESD事件期间。

2. 发明授权

US6078487A Electro-static discharge protection device having a modulated control input terminal 失效
标题翻译：具有调制控制输入端子的静电放电保护装置
公开(公告)号：US6078487A
公开(公告)日：2000-06-20
申请号：US853840
申请日：1997-05-09
申请人： Hamid Partovi , Kaizad R. Mistry , David B. Krakauer , William A. McGee
发明人： Hamid Partovi , Kaizad R. Mistry , David B. Krakauer , William A. McGee
IPC分类号： H03K17/0814 , H02H9/00
CPC分类号： H01L27/0266 , H03K17/08142
摘要： A circuit which protects an integrated circuit (IC) device from damage due to electrostatic discharge (ESD). The protection circuit includes an N-channel metal oxide semiconductor field effect transistor (MOSFET) clamping device and a gate modulation circuit. The source and drain of the MOSFET clamp are connected between an input/output (I/O) pad of the IC and a ground reference voltage. During normal operation of the IC, the gate modulation circuit disables the MOSFET clamp by connecting its gate terminal to a ground reference voltage. This permits signal voltages to pass between the I/O pad and any operating circuits connected to the pad. During an ESD event, the gate modulation circuit connects the gate to the I/O pad, which enables the MOSFET clamp, causing any ESD voltages and resulting currents to be shunted through the MOSFET clamp to ground. As a result, the ESD clamp reaches its clamped-to snapback voltage via an increase in MOSFET channel current, and not via junction breakdown. This insures that the ESD clamp reaches its snapback voltage before the onset of junction breakdown in the operating circuits. The circuit is especially useful in integrated circuits where the gate oxide of a standard ESD clamp transistor is too thin to protect the operating logic from I/O signal voltages that are greater than the supply voltage used for the operating logic circuits.
摘要翻译：保护集成电路（IC）器件免受静电放电（ESD）损坏的电路。保护电路包括N沟道金属氧化物半导体场效应晶体管（MOSFET）钳位装置和栅极调制电路。 MOSFET钳位的源极和漏极连接在IC的输入/输出（I / O）焊盘和接地参考电压之间。在IC的正常工作期间，栅极调制电路通过将其栅极端子连接到接地参考电压来禁用MOSFET钳位。这允许信号电压在I / O焊盘和连接到焊盘的任何操作电路之间通过。在ESD事件期间，栅极调制电路将栅极连接到I / O焊盘，这使得MOSFET钳位能够使任何ESD电压和所产生的电流通过MOSFET钳位分流到地。因此，ESD钳位通过MOSFET沟道电流的增加而不是通过结击穿而达到其钳位到快速恢复电压。这确保了ESD钳位在工作电路结点击穿开始之前达到其回跳电压。该电路在集成电路中特别有用，其中标准ESD钳位晶体管的栅极氧化物太薄，无法保护操作逻辑免受大于操作逻辑电路所用电源电压的I / O信号电压的影响。

3. 发明授权

US5546354A Static random access memory having tunable-self-timed control logic circuits 失效
标题翻译：具有可调谐自定时控制逻辑电路的静态随机存取存储器
公开(公告)号：US5546354A
公开(公告)日：1996-08-13
申请号：US270190
申请日：1994-07-01
申请人： Hamid Partovi , Steven Butler , Luan Tran
发明人： Hamid Partovi , Steven Butler , Luan Tran
IPC分类号： G11C7/22 , G11C8/18 , G11C7/00
CPC分类号： G11C7/22 , G11C8/18
摘要： A self-timed logic device which produces internal control and timing signals in response to an external signal is described. The circuit includes means responsive to a pulse signal for providing control and timing signals and means responsive to a change in state of a signal fed to said device for providing said pulse signal. The means for providing said pulse further includes means for selectively changing timing characteristics of said device in response to external tuning signals fed to the device. In a preferred embodiment the logic device is a static random access memory.
摘要翻译：描述了响应于外部信号产生内部控制和定时信号的自定时逻辑器件。该电路包括响应于脉冲信号以提供控制和定时信号的装置，以及响应馈送到所述装置的信号的状态改变以提供所述脉冲信号的装置。用于提供所述脉冲的装置还包括用于响应于馈送到装置的外部调谐信号选择性地改变所述装置的定时特性的装置。在优选实施例中，逻辑设备是静态随机存取存储器。

4. 发明授权

US5353424A Fast tag compare and bank select in set associative cache 失效
标题翻译：快速标签比较和集合相关缓存中的存储区选择
公开(公告)号：US5353424A
公开(公告)日：1994-10-04
申请号：US794865
申请日：1991-11-19
申请人： Hamid Partovi , William R. Wheeler , Michael Leary , Michael A. Case , Steven Butler , Rajesh Khanna
发明人： Hamid Partovi , William R. Wheeler , Michael Leary , Michael A. Case , Steven Butler , Rajesh Khanna
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F12/0864
摘要： A tag comparator and bank selector for a set-associative cache in a computer system operates in a minimum time so that a cache hit or miss signal is generated early in a memory cycle. The data memory of the cache has two (or more) banks, with a tag store for each bank, and the two banks are accessed separately and in parallel using the index (low order address bits) while the tag translation is in progress. Two bit-by-bit tag compares are performed, one for each tag store, producing two multibit match indications, one bit for each tag bit in each tag store. These two match indications are applied to two separate dynamic NOR gates, and the two outputs applied to a logic circuit to detect a hit and generate a bank-select output. There are four possible outcomes from the compare operation: both banks miss, left bank hits, right bank hits, and both banks hit. The later condition indicates a possible ambiguity, and neither data item should be used, so a miss is signalled. The comparator is in large part self-timed using a flow-through design, as distinguished from being enabled on clock edges. Delay elements in the bank select logic allow the banks to be timed against each other, and current limiters are employed to equalize the timing of miss signals, regardless of the number of match lines switching high (which is data dependent). An address producing 19-of-20 match bits will result in a NOR gate output of about the same timing as an address producing no match bits, even though the former will turn on only one transistor to discharge the precharged output node of the NOR gate, whereas the later will turn on twenty paths for discharge. Although a two-way set associative cache is shown herein as an example embodiment, one of the features of the invention is that higher levels of associativity, e.g., four-way and eight-way, are equally well accommodated.
摘要翻译：用于计算机系统中的组相关高速缓存的标签比较器和存储体选择器在最小时间内操作，使得在存储器周期中早期产生高速缓存命中或未命中信号。高速缓存的数据存储器具有两个（或更多个）存储体，每个存储体具有标签存储，并且当标签转换正在进行时，使用索引（低位地址位）分开存取和并行访问两个存储体。执行两个逐位标签比较，每个标签存储一个，产生两个多位匹配指示，每个标签存储中每个标签位一位。这两个匹配指示被应用于两个单独的动态NOR门，并且两个输出被施加到逻辑电路以检测命中并产生一个存储体选择输出。比较操作有四个可能的结果：两家银行错失，左岸点击，右岸点击，两家银行都受到打击。后面的条件表示可能的模糊性，并且都不应该使用数据项，所以发出了错误信号。使用流通设计，比较器在很大程度上是自定时的，与时钟边沿不同。银行选择逻辑中的延迟元素允许银行彼此定时，并且采用电流限制器来均衡缺失信号的定时，而不管匹配线的数量如何切换高（这取决于数据）。产生20位20位匹配位的地址将导致与不产生不匹配位的地址大致相同的定时的或非门输出，即使前者将仅接通一个晶体管来放电NOR门的预充电输出节点，而后来将打开二十条出路。尽管本文中示出了双向组关联高速缓存作为示例实施例，但是本发明的特征之一是更高级别的关联性，例如四路和八路同样适应。

5. 发明授权

US07813289B2 Electrical idle detection circuit including input signal rectifier 有权
标题翻译：电气怠速检测电路包括输入信号整流器
公开(公告)号：US07813289B2
公开(公告)日：2010-10-12
申请号：US11346064
申请日：2006-02-02
申请人： Hamid Partovi , Karthik Gopalakrishnan , Luca Ravezzi
发明人： Hamid Partovi , Karthik Gopalakrishnan , Luca Ravezzi
IPC分类号： H04L1/00
CPC分类号： G06F13/4072
摘要： An electrical idle detection circuit including a full wave rectifier and a first amplifier. The full wave rectifier is configured to receive differential input signals and provide a rectified output signal based on the differential input signals. The first amplifier is configured to receive a first input signal based on the rectified output signal and a second input signal based on a reference signal. The first amplifier is configured to provide an output signal that indicates the differential input signals are one of active and in electrical idle based on the first input signal and the second input signal.
摘要翻译：一种包括全波整流器和第一放大器的电怠速检测电路。全波整流器配置为接收差分输入信号，并根据差分输入信号提供整流输出信号。第一放大器被配置为基于经整流的输出信号接收第一输入信号，并且基于参考信号接收第二输入信号。第一放大器被配置为提供输出信号，其基于第一输入信号和第二输入信号来指示差分输入信号是有效和电空闲之一。

6. 发明授权

US07733815B2 Data sampler including a first stage and a second stage 失效
标题翻译：数据采样器包括第一级和第二级
公开(公告)号：US07733815B2
公开(公告)日：2010-06-08
申请号：US11494848
申请日：2006-07-28
申请人： Karthik Gopalakrishnan , Luca Ravezzi , Sivaraman Chokkalingam , Edoardo Prete , Hamid Partovi
发明人： Karthik Gopalakrishnan , Luca Ravezzi , Sivaraman Chokkalingam , Edoardo Prete , Hamid Partovi
IPC分类号： H04B3/52 , H03F3/04
CPC分类号： H03M1/1245
摘要： A data sampler including a first stage and a second stage. The first stage is configured to receive differential signals and provide a first edge rate in a first output signal and a second edge rate in a second output signal based on the differential signals. The second stage is configured to amplify the difference between the first output signal and the second output signal to provide regenerated output signals. The second stage provides a third edge rate in a first internal signal and a fourth edge rate in a second internal signal based on the first edge rate and the second edge rate.
摘要翻译：数据采样器，包括第一级和第二级。第一级被配置为基于差分信号接收差分信号并提供第一输出信号中的第一边沿速率和第二输出信号中的第二边缘速率。第二级被配置为放大第一输出信号和第二输出信号之间的差以提供再生的输出信号。第二级基于第一边沿速率和第二边缘速率，提供第一内部信号中的第三边沿速率和第二内部信号中的第四边缘速率。

7. 发明申请

US20090180335A1 INTEGRATED CIRCUIT WITH REDUCED POINTER UNCERTAINLY 审中-公开
标题翻译：集成电路与减少指针不确定
公开(公告)号：US20090180335A1
公开(公告)日：2009-07-16
申请号：US12014452
申请日：2008-01-15
申请人： Sivaraman Chokkalingam , Hamid Partovi , Luca Ravezzi
发明人： Sivaraman Chokkalingam , Hamid Partovi , Luca Ravezzi
IPC分类号： G11C7/00 , H03L7/00 , G11C8/00
CPC分类号： G11C7/22 , G11C5/00 , G11C7/222 , H03L7/06
摘要： One embodiment provides an integrated circuit including a first circuit and a second circuit. The first circuit is configured to obtain a sample of a first clock via a second clock and provide a selected clock from multiple clocks based on the sample. The second circuit is configured to provide a first pointer clock based on the first clock and a second pointer clock based on the selected clock. An edge of the second pointer clock relative to an edge of the first pointer clock is limited to an uncertainty range of within one-half a first pointer clock cycle.
摘要翻译：一个实施例提供了包括第一电路和第二电路的集成电路。第一电路被配置为经由第二时钟获得第一时钟的采样，并且基于该采样从多个时钟提供选定的时钟。第二电路被配置为基于第一时钟提供第一指针时钟，并且基于所选择的时钟提供第二指针时钟。相对于第一指针时钟的边缘的第二指针时钟的边缘被限制在第一指针时钟周期的二分之一内的不确定性范围。

8. 发明申请

US20090160559A1 INTEGRATED CIRCUIT INCLUDING IMPEDANCE TO PROVIDE SYMMETRICAL DIFFERENTIAL SIGNALS 审中-公开
标题翻译：集成电路，包括阻抗提供对称差分信号
公开(公告)号：US20090160559A1
公开(公告)日：2009-06-25
申请号：US11960036
申请日：2007-12-19
申请人： Luca Ravezzi , Hamid Partovi
发明人： Luca Ravezzi , Hamid Partovi
IPC分类号： H03F3/04
CPC分类号： H03F3/45183 , H03F2203/45148 , H03F2203/45166 , H03H11/32
摘要： One embodiment provides an integrated circuit including an input stage and an impedance. The input stage is configured to receive a single-ended input signal and provide a differential output signal. The impedance is configured to receive the single-ended input signal and provide compensation to the input stage to provide symmetrical differential signals in the differential output signal.
摘要翻译：一个实施例提供了包括输入级和阻抗的集成电路。输入级被配置为接收单端输入信号并提供差分输出信号。阻抗被配置为接收单端输入信号，并向输入级提供补偿，以在差分输出信号中提供对称的差分信号。

9. 发明授权

US6137126A Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer 有权
标题翻译：使用LDD间隔物的低介电常数材料来减少门到局部互连电容的方法
公开(公告)号：US6137126A
公开(公告)日：2000-10-24
申请号：US375499
申请日：1999-08-17
申请人： Steven C. Avanzino , Minh Van Ngo , Angela T. Hui , Chun Jiang , Hamid Partovi
发明人： Steven C. Avanzino , Minh Van Ngo , Angela T. Hui , Chun Jiang , Hamid Partovi
IPC分类号： H01L21/336 , H01L21/768 , H01L29/49 , H01L29/72 , H01L27/10
CPC分类号： H01L29/6659 , H01L21/76895 , H01L29/4983 , Y10S257/90
摘要： The capacitance between a gate electrode of a transistor and local interconnect is reduced by employing SiC sidewall spacers on the side surfaces of the gate electrode when forming the source/drain regions with shallow extensions. Embodiments include forming SiC sidewall spacers at a width of about 500 .ANG. to about 800 .ANG. having a dielectric constant of less than about 3.2, depositing a silicon oxide inter-dielectric layer, and forming the local interconnect through the inter-dielectric layer. The resulting composite dielectric constant between the gate electrode and local interconnect is about 4.2 to about 4.7.
摘要翻译：当形成具有浅延伸的源极/漏极区域时，通过在栅电极的侧表面上使用SiC侧壁间隔来减小晶体管的栅电极和局部互连之间的电容。实施例包括将SiC侧壁间隔物形成为具有小于约3.2的介电常数的约500安培的宽度至约800安培角，沉积氧化硅介电层，以及通过介电层形成局部互连。栅电极和局部互连之间的所得复合介电常数为约4.2至约4.7。

10. 发明授权

US6081136A Dynamic NOR gates for NAND decode 失效
标题翻译：用于NAND解码的动态NOR门
公开(公告)号：US6081136A
公开(公告)日：2000-06-27
申请号：US993335
申请日：1997-12-19
申请人： Rajesh Khanna , Hamid Partovi
发明人： Rajesh Khanna , Hamid Partovi
IPC分类号： H03K19/096 , H03K19/003
CPC分类号： H03K19/0963
摘要： A NOR gate pair includes a first and second NOR gate, each with a plurality of inputs and an output. A first NAND gate has a first input coupled to the output of the first NOR gate, a second input coupled to the output of the second NOR gate through a first input inverter, and an output. A second NAND gate has a first input coupled to the output of the second NOR gate, a second input coupled to the output of the first NOR gate through a second input inverter, and an output. A first output inverter is coupled to the output of the first NAND gate and a second output inverter is coupled to the output of the second NAND gate. This configuration assures that NOR gates used in a one-hot-decode decoder will all have logic-low outputs during a precharge phase.
摘要翻译： NOR门对包括第一和第二NOR门，每个具有多个输入和输出。第一NAND门具有耦合到第一或非门的输出的第一输入端，通过第一输入反相器耦合到第二或非门的输出的第二输入和输出。第二与非门具有耦合到第二或非门的输出的第一输入，通过第二输入反相器耦合到第一或非门的输出的第二输入和输出。第一输出反相器耦合到第一NAND门的输出，第二输出反相器耦合到第二NAND门的输出。该配置确保在一个热解码解码器中使用的或非门将在预充电阶段期间都具有逻辑低输出。

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