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1. 发明授权

US07453315B2 Active inductive load that enhances circuit bandwidth 有权
标题翻译：有源电感负载，增强电路带宽
公开(公告)号：US07453315B2
公开(公告)日：2008-11-18
申请号：US11411343
申请日：2006-04-26
申请人： Luca Ravezzi , Karthik Gopalakrishnan
发明人： Luca Ravezzi , Karthik Gopalakrishnan
IPC分类号： H03H11/24
CPC分类号： H03F1/42
摘要： An active load including a current source, a first resistive element, and a switch. The current source is configured to provide a bias current and the first resistive element is configured to receive the bias current and provide a bias voltage. The switch has an input and an output and is configured to receive a drive voltage at the input, receive the bias voltage between the input and the output, provide an output voltage at the output that is sufficiently different than the drive voltage to maintain headroom, and provide an inductive impedance that enhances circuit bandwidth.
摘要翻译：包括电流源，第一电阻元件和开关的有源负载。电流源被配置为提供偏置电流，并且第一电阻元件被配置为接收偏置电流并提供偏置电压。开关具有输入和输出，并被配置为在输入端接收驱动电压，接收输入和输出之间的偏置电压，在输出端提供足够不同于驱动电压的输出电压，以保持净空，并提供增强电路带宽的电感阻抗。

2. 发明申请

US20080024215A1 Data sampler including a first stage and a second stage 失效
标题翻译：数据采样器包括第一级和第二级
公开(公告)号：US20080024215A1
公开(公告)日：2008-01-31
申请号：US11494848
申请日：2006-07-28
申请人： Karthik Gopalakrishnan , Luca Ravezzi , Sivaraman Chokkalingam , Edoardo Prete , Hamid Partovi
发明人： Karthik Gopalakrishnan , Luca Ravezzi , Sivaraman Chokkalingam , Edoardo Prete , Hamid Partovi
IPC分类号： H03F3/04
CPC分类号： H03M1/1245
摘要： A data sampler including a first stage and a second stage. The first stage is configured to receive differential signals and provide a first edge rate in a first output signal and a second edge rate in a second output signal based on the differential signals. The second stage is configured to amplify the difference between the first output signal and the second output signal to provide regenerated output signals. The second stage provides a third edge rate in a first internal signal and a fourth edge rate in a second internal signal based on the first edge rate and the second edge rate.
摘要翻译：数据采样器，包括第一级和第二级。第一级被配置为基于差分信号接收差分信号并提供第一输出信号中的第一边沿速率和第二输出信号中的第二边缘速率。第二级被配置为放大第一输出信号和第二输出信号之间的差以提供再生的输出信号。第二级基于第一边沿速率和第二边缘速率，提供第一内部信号中的第三边沿速率和第二内部信号中的第四边缘速率。

3. 发明申请

US20070180281A1 Electrical idle detection circuit including input signal rectifier 有权
标题翻译：电气怠速检测电路包括输入信号整流器
公开(公告)号：US20070180281A1
公开(公告)日：2007-08-02
申请号：US11346064
申请日：2006-02-02
申请人： Hamid Partovi , Karthik Gopalakrishnan , Luca Ravezzi
发明人： Hamid Partovi , Karthik Gopalakrishnan , Luca Ravezzi
IPC分类号： G06F1/32
CPC分类号： G06F13/4072
摘要： An electrical idle detection circuit including a full wave rectifier and a first amplifier. The full wave rectifier is configured to receive differential input signals and provide a rectified output signal based on the differential input signals. The first amplifier is configured to receive a first input signal based on the rectified output signal and a second input signal based on a reference signal. The first amplifier is configured to provide an output signal that indicates the differential input signals are one of active and in electrical idle based on the first input signal and the second input signal.
摘要翻译：一种包括全波整流器和第一放大器的电怠速检测电路。全波整流器配置为接收差分输入信号，并根据差分输入信号提供整流输出信号。第一放大器被配置为基于经整流的输出信号接收第一输入信号，并且基于参考信号接收第二输入信号。第一放大器被配置为提供输出信号，其基于第一输入信号和第二输入信号来指示差分输入信号是有效和电空闲之一。

4. 发明授权

US08604854B1 Pseudo single-phase flip-flop (PSP-FF) 有权
标题翻译：伪单相触发器（PSP-FF）
公开(公告)号：US08604854B1
公开(公告)日：2013-12-10
申请号：US13412679
申请日：2012-03-06
申请人： Hamid Partovi , Alfred Yeung , Luca Ravezzi , John Ngai
发明人： Hamid Partovi , Alfred Yeung , Luca Ravezzi , John Ngai
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356113
摘要： Disclosed herein is a pseudo single-phase flip-flop. The master section includes a pre-dissipation stage and a first keeper. The pre-dissipation stage discharges the first keeper to the mDb second binary value, and selectively charges the first keeper with the mDb first binary value in the master pass mode. The pre-dissipation stage selectively prevents the first keeper from charging to the mDb first binary value in response to one of the clock phases. The slave section includes a pre-charge stage, a second keeper, a post-dissipation stage, and a third keeper. The second keeper maintains a first binary value in a slave pass mode when the mDb signal has a second binary value. The second keeper supports the second binary value in the slave pass mode when the mDb signal has the first binary value. The third keeper maintains the Q signal binary value during the slave hold mode.
摘要翻译：这里公开了伪单相触发器。主部分包括预耗散阶段和第一保持器。预耗散级将第一保持器放电到mDb第二二进制值，并且在主通过模式中以mDb第一二进制值选择性地对第一保持器充电。响应于时钟相位之一，预耗散级选择性地防止第一保持器充电到mDb第一二进制值。从部分包括预充电阶段，第二保持器，后消耗阶段和第三保持器。当mDb信号具有第二二进制值时，第二保持器保持从通模式中的第一二进制值。当mDb信号具有第一二进制值时，第二保持器支持从通模式中的第二二进制值。第三保持器在从机保持模式期间保持Q信号二进制值。

5. 发明申请

US20090164165A1 INTEGRATED CIRCUIT INCLUDING CALIBRATION CIRCUIT 有权
标题翻译：集成电路，包括校准电路
公开(公告)号：US20090164165A1
公开(公告)日：2009-06-25
申请号：US11960069
申请日：2007-12-19
申请人： Russell Homer , Luca Ravezzi , Hamid Partovi
发明人： Russell Homer , Luca Ravezzi , Hamid Partovi
IPC分类号： G01R35/00
CPC分类号： G11C7/1051 , G11C7/02 , G11C7/1057 , G11C29/02 , G11C29/022 , G11C29/50008 , G11C2207/2254
摘要： One embodiment provides an integrated circuit including a first circuit, a second circuit, and a third circuit. The first circuit is configured to provide a calibrated signal. The second circuit is configured to low pass filter the calibrated signal and provide a filtered calibrated signal. The third circuit is configured to provide a control signal and store the control signal based on the filtered calibrated signal. The third circuit averages stored controlled signals to provide a calibration result.
摘要翻译：一个实施例提供了包括第一电路，第二电路和第三电路的集成电路。第一电路被配置为提供校准信号。第二电路被配置为对经校准的信号进行低通滤波并提供滤波的校准信号。第三电路被配置为提供控制信号并且基于滤波的校准信号来存储控制信号。存储控制信号的第三个电路平均提供校准结果。

6. 发明申请

US20070252618A1 Signal converter circuit 审中-公开
标题翻译：信号转换电路
公开(公告)号：US20070252618A1
公开(公告)日：2007-11-01
申请号：US11413315
申请日：2006-04-28
申请人： Karthik Gopalakrishnan , Otto Schumacher , Luca Ravezzi , Andreas Blum , Hamid Partovi
发明人： Karthik Gopalakrishnan , Otto Schumacher , Luca Ravezzi , Andreas Blum , Hamid Partovi
IPC分类号： H03K19/094
CPC分类号： H03K19/0185 , H03K19/09432
摘要： A signal converter circuit including an input circuit and an output circuit. The input circuit is configured to receive current mode logic signals and provide differential input signals based on the current mode logic signals. The output circuit is configured to receive the differential input signals and provide rail-to-rail output signals based on the differential input signals. The output circuit is configured to switch the rail-to-rail output signals in response to a common edge type in each of the differential input signals.
摘要翻译：一种包括输入电路和输出电路的信号转换器电路。输入电路被配置为接收电流模式逻辑信号并且基于当前模式逻辑信号提供差分输入信号。输出电路被配置为接收差分输入信号并且基于差分输入信号提供轨到轨输出信号。输出电路被配置为响应于每个差分输入信号中的公共边缘类型来切换轨到轨输出信号。

7. 发明授权

US08421514B1 Hazard-free minimal-latency flip-flop (HFML-FF) 有权
标题翻译：无危险的最小延迟触发器（HFML-FF）
公开(公告)号：US08421514B1
公开(公告)日：2013-04-16
申请号：US13225044
申请日：2011-09-02
申请人： Alfred Yeung , Hamid Partovi , Luca Ravezzi , John Ngai
发明人： Alfred Yeung , Hamid Partovi , Luca Ravezzi , John Ngai
IPC分类号： H03K3/289
CPC分类号： H03K3/013 , H03K3/356156 , H03K3/35625
摘要： A hazard-free minimal-latency flip-flop (HFML-FF) is provided. A master latch includes an input to accept a D1 signal, an input to accept a clock signal, an input to accept an inverted shadow-D2 signal, and an output to supply a D2 signal. The master latch has an input to accept a shadow-D1 signal, an input to accept the clock signal, and an output to supply a shadow-D2 signal and the inverted shadow-D2 signal. The slave latch has an input to accept the D2 signal, an input to accept the clock signal, an input to accept an inverted shadow-Q signal, and an output to supply a Q signal. The slave latch has an input to accept either the D2 signal or the shadow-D2 signal, an input to accept the clock signal, and an output to supply a shadow-Q signal and the inverted shadow-Q signal. The design may use clocked inverters or pass gates.
摘要翻译：提供无危险的最小延迟触发器（HFML-FF）。主锁存器包括接收D1信号的输入端，接受时钟信号的输入端，接收反相阴影D2信号的输入端和提供D2信号的输出端。主锁存器具有接受阴影D1信号的输入端，接受时钟信号的输入端，以及提供阴影D2信号和反相阴影D2信号的输出端。从锁存器具有接收D2信号的输入端，接受时钟信号的输入端，接收反相阴影Q信号的输入端和提供Q信号的输出端。从锁存器具有接收D2信号或阴影D2信号的输入端，用于接受时钟信号的输入端和用于提供阴影Q信号和反相阴影Q信号的输出。该设计可以使用时钟反相器或通过门。

8. 发明授权

US07991573B2 Integrated circuit including calibration circuit 有权
标题翻译：集成电路包括校准电路
公开(公告)号：US07991573B2
公开(公告)日：2011-08-02
申请号：US11960069
申请日：2007-12-19
申请人： Russell Homer , Luca Ravezzi , Hamid Partovi
发明人： Russell Homer , Luca Ravezzi , Hamid Partovi
IPC分类号： G01R35/00
CPC分类号： G11C7/1051 , G11C7/02 , G11C7/1057 , G11C29/02 , G11C29/022 , G11C29/50008 , G11C2207/2254
摘要： One embodiment provides an integrated circuit including a first circuit, a second circuit, and a third circuit. The first circuit is configured to provide a calibrated signal. The second circuit is configured to low pass filter the calibrated signal and provide a filtered calibrated signal. The third circuit is configured to provide a control signal and store the control signal based on the filtered calibrated signal. The third circuit averages stored controlled signals to provide a calibration result.
摘要翻译：一个实施例提供了包括第一电路，第二电路和第三电路的集成电路。第一电路被配置为提供校准信号。第二电路被配置为对经校准的信号进行低通滤波并提供滤波的校准信号。第三电路被配置为提供控制信号并且基于滤波的校准信号来存储控制信号。存储控制信号的第三个电路平均提供校准结果。

9. 发明申请

US20110012685A1 Wide-band Low-voltage IQ-generating Ring-oscillator-based CMOS VCO 审中-公开
标题翻译：宽带低压IQ生成环形振荡器的CMOS VCO
公开(公告)号：US20110012685A1
公开(公告)日：2011-01-20
申请号：US12684164
申请日：2010-01-08
申请人： Hamid Partovi , Luca Ravezzi
发明人： Hamid Partovi , Luca Ravezzi
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A voltage controlled oscillator circuit includes first and second power rails, a control voltage rail, an input terminal, and an output terminal. A plurality of domino stages are series connected in a ring, with each of the domino stages being connected across the first and second power rails and being responsive to the control voltage rail. A plurality of feedback paths is provided with each path connected to enable one of the plurality of domino stages to input a feedback output signal to a preceding serially connected domino stage. A reset signal is asserted to place the domino stages in a post charge state and deasserted to allow the domino stages to begin producing an oscillating signal.
摘要翻译：压控振荡器电路包括第一和第二电源轨，控制电压轨，输入端和输出端。多个多米诺骨牌级串联连接在一个环中，其中每个多米诺骨牌级跨越第一和第二电力轨道连接并响应控制电压轨。提供多个反馈路径，每个路径被连接以使得多个多米诺骨牌阶段中的一个能够将反馈输出信号输入到先前的串行连接的多米诺骨牌阶段。复位信号被断言以将多米诺骨牌阶段置于后付费状态，并且被断言以允许多米诺骨牌阶段开始产生振荡信号。

10. 发明申请

US20070252642A1 Active load 有权
标题翻译：有功负载
公开(公告)号：US20070252642A1
公开(公告)日：2007-11-01
申请号：US11411343
申请日：2006-04-26
申请人： Luca Ravezzi , Karthik Gopalakrishnan
发明人： Luca Ravezzi , Karthik Gopalakrishnan
IPC分类号： H03F3/14
CPC分类号： H03F1/42
摘要： An active load including a current source, a first resistive element, and a switch. The current source is configured to provide a bias current and the first resistive element is configured to receive the bias current and provide a bias voltage. The switch has an input and an output and is configured to receive a drive voltage at the input, receive the bias voltage between the input and the output, provide an output voltage at the output that is sufficiently different than the drive voltage to maintain headroom, and provide an inductive impedance that enhances circuit bandwidth.
摘要翻译：包括电流源，第一电阻元件和开关的有源负载。电流源被配置为提供偏置电流，并且第一电阻元件被配置为接收偏置电流并提供偏置电压。开关具有输入和输出，并被配置为在输入端接收驱动电压，接收输入和输出之间的偏置电压，在输出端提供与驱动电压充分不同的输出电压，以保持净空，并提供增强电路带宽的电感阻抗。

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