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1. 发明授权

US06356250B1 Matrix addressable display with electrostatic discharge protection 失效
标题翻译：具有静电放电保护的矩阵可寻址显示
公开(公告)号：US06356250B1
公开(公告)日：2002-03-12
申请号：US09640826
申请日：2000-08-16
申请人： David A. Cathey , Glen E. Hush , Manny K. F. Ma , Craig M. Dunham , David A. Zimlich
发明人： David A. Cathey , Glen E. Hush , Manny K. F. Ma , Craig M. Dunham , David A. Zimlich
IPC分类号： G09G328
CPC分类号： H01J31/127 , H01J3/022 , H01J2201/319 , H01J2329/92
摘要： A field emission display includes electrostatic discharge protection circuits coupled to an emitter substrate and an extraction grid. In the preferred embodiment, the electrostatic discharge circuit includes diodes reverse biased between grid sections and a first reference potential or between row lines and a second reference potential. The diodes provide a current path to discharge static voltage and thereby prevent a high voltage differential from being maintained between the emitter sets and the extraction grids. The diodes thereby prevent the emitter sets from emitting electrons at a high rate that may damage or destroy the emitter sets. In one embodiment, the diodes are coupled directly between the grid sections and the row lines. In one embodiment, the diodes are formed in an insulative layer carrying the grid sections. In another embodiment, the diodes are integrated into the emitter substrate.
摘要翻译：场发射显示器包括耦合到发射极衬底和提取栅极的静电放电保护电路。在优选实施例中，静电放电电路包括在网格部分和第一参考电位之间或在行线和第二参考电位之间反向偏置的二极管。二极管提供电流路径来放电静电压，从而防止在发射极组和提取栅之间保持高电压差。因此，二极管可防止发射极组以可能损坏或破坏发射极组的高速率发射电子。在一个实施例中，二极管直接连接在网格部分和行线之间。在一个实施例中，二极管形成在承载网格部分的绝缘层中。在另一个实施例中，二极管被集成到发射器衬底中。

2. 发明授权

US06266034B1 Matrix addressable display with electrostatic discharge protection 失效
标题翻译：具有静电放电保护的矩阵可寻址显示
公开(公告)号：US06266034B1
公开(公告)日：2001-07-24
申请号：US09181232
申请日：1998-10-27
申请人： David A. Cathey , Glen E. Hush , Manny K. F. Ma , Craig M. Dunham , David A. Zimlich
发明人： David A. Cathey , Glen E. Hush , Manny K. F. Ma , Craig M. Dunham , David A. Zimlich
IPC分类号： G09G322
CPC分类号： H01J31/127 , H01J3/022 , H01J2201/319 , H01J2329/92
摘要： A field emission display includes electrostatic discharge protection circuits coupled to an emitter substrate and an extraction grid. In the preferred embodiment, the electrostatic discharge circuit includes diodes reverse biased between grid sections and a first reference potential or between row lines and a second reference potential. The diodes provide a current path to discharge static voltage and thereby prevent a high voltage differential from being maintained between the emitter sets and the extraction grids. The diodes thereby prevent the emitter sets from emitting electrons at a high rate that may damage or destroy the emitter sets. In one embodiment, the diodes are coupled directly between the grid sections and the row lines. In one embodiment, the diodes are formed in an insulative layer carrying the grid sections. In another embodiment, the diodes are integrated into the emitter substrate.
摘要翻译：场发射显示器包括耦合到发射极衬底和提取栅极的静电放电保护电路。在优选实施例中，静电放电电路包括在网格部分和第一参考电位之间或在行线和第二参考电位之间反向偏置的二极管。二极管提供电流路径来放电静电压，从而防止在发射极组和提取栅之间保持高电压差。因此，二极管可防止发射极组以可能损坏或破坏发射极组的高速率发射电子。在一个实施例中，二极管直接连接在网格部分和行线之间。在一个实施例中，二极管形成在承载网格部分的绝缘层中。在另一个实施例中，二极管被集成到发射器衬底中。

3. 发明授权

US5844370A Matrix addressable display with electrostatic discharge protection 失效
公开(公告)号：US5844370A
公开(公告)日：1998-12-01
申请号：US706295
申请日：1996-09-04
申请人： David A. Cathey , Glen E. Hush , Manny K. F. Ma , Craig M. Dunham , David A. Zimlich
发明人： David A. Cathey , Glen E. Hush , Manny K. F. Ma , Craig M. Dunham , David A. Zimlich
IPC分类号： H01J29/04 , G09G3/20 , G09G3/22 , H01J3/02 , H01J31/12 , H01J19/24
CPC分类号： H01J31/127 , H01J3/022 , H01J2201/319 , H01J2329/92
摘要： A field emission display includes electrostatic discharge protection circuits coupled to an emitter substrate and an extraction grid. In the preferred embodiment, the electrostatic discharge circuit includes diodes reverse biased between grid sections and a first reference potential or between row lines and a second reference potential. The diodes provide a current path to discharge static voltage and thereby prevent a high voltage differential from being maintained between the emitter sets and the extraction grids. The diodes thereby prevent the emitter sets from emitting electrons at a high rate that may damage or destroy the emitter sets. In one embodiment, the diodes are coupled directly between the grid sections and the row lines. In one embodiment, the diodes are formed in an insulative layer carrying the grid sections. In another embodiment, the diodes are integrated into the emitter substrate.

4. 发明授权

US07253064B2 Cascode I/O driver with improved ESD operation 有权
标题翻译：串行I / O驱动器，具有改进的ESD操作
公开(公告)号：US07253064B2
公开(公告)日：2007-08-07
申请号：US10853538
申请日：2004-05-25
申请人： Michael D. Chaine , Manny K. F. Ma
发明人： Michael D. Chaine , Manny K. F. Ma
IPC分类号： H01L21/336
CPC分类号： H01L29/7831 , H01L27/0266 , H01L29/0649 , H01L29/0692 , H01L29/41725
摘要： A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An system is described that includes an I/O driver in parallel with an ESD device. In an embodiment, the I/O driver may assist the ESD device in discharging electrostatic, after the ESD begins conducting.
摘要翻译：描述了包括形成在两个晶体管之间的共享区域中的屏障的级联I / O驱动器。屏障区域允许I / O驱动程序设计为主要满足I / O要求。因此，实现了改进的操作速度。描述了包括与ESD装置并联的I / O驱动器的系统。在一个实施例中，在ESD开始导通之后，I / O驱动器可以辅助静电装置放电静电。

5. 发明授权

US06600215B1 Method and apparatus for coupling a semiconductor die to die terminals 失效
公开(公告)号：US06600215B1
公开(公告)日：2003-07-29
申请号：US09054275
申请日：1998-04-02
申请人： Aaron Schoenfeld , Manny K. F. Ma , Larry D. Kinsman , J. Mike Brooks , Timothy J. Allen
发明人： Aaron Schoenfeld , Manny K. F. Ma , Larry D. Kinsman , J. Mike Brooks , Timothy J. Allen
IPC分类号： H01L2348
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/49838 , H01L23/642 , H01L23/645 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48599 , H01L2224/48699 , H01L2224/49171 , H01L2224/49433 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01079 , H01L2924/014 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2924/00012
摘要： A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals. The first and second conductive members may each have an intermediate portion between the first and second end portions thereof that is narrower than the second end portions thereof, and the conductive members may be staggered by axially offsetting the second end portion of the second conductive member from the second end portion of the first conductive member.

6. 发明授权

US6069492A Voltage compensating CMOS input buffer circuit 失效
标题翻译：电压补偿CMOS输入缓冲电路
公开(公告)号：US6069492A
公开(公告)日：2000-05-30
申请号：US925376
申请日：1997-09-08
申请人： Joseph C. Sher , Manny K. F. Ma
发明人： Joseph C. Sher , Manny K. F. Ma
IPC分类号： H03K19/003 , H03K19/0185 , H03K17/0185
CPC分类号： H03K19/018521 , H03K19/00384
摘要： A voltage compensating CMOS input buffer converts input TTL signals to CMOS logic levels, and compensates for changing supply voltage by using a n-channel transistor to vary the effective size ratio of pairs p-channel to n-channel transistors making up an input inverter. The compensating transistor becomes operable with increasing supply voltage to help the n-channel input inverter transistors offset the p-channel input inverter transistors whose trip points would otherwise have been increased by increasing power supply voltage. As the power supply voltage decreases, the compensating transistor turns off, returning the input inverter to its original size ratio. The gate of the compensating transistor is coupled to the supply voltage through two diodes to control the amount of current flowing through the compensating transistor. Further trip point transistors in series with the compensating transistor have their gates coupled to the input signals to help stabilize the trip points. An output stage inverter provides the CMOS logic levels from the output of the input inverter.
摘要翻译：电压补偿CMOS输入缓冲器将输入TTL信号转换为CMOS逻辑电平，并通过使用n沟道晶体管来补偿变化的电源电压，从而将p沟道对的有效尺寸比改变成组成输入反相器的n沟道晶体管。补偿晶体管可以以增加的电源电压工作，以帮助n沟道输入反相器晶体管偏移通过增加电源电压而其跳变点将被增加的p沟道输入反相器晶体管。随着电源电压的降低，补偿晶体管关闭，使输入逆变器返回原来的大小比例。补偿晶体管的栅极通过两个二极管耦合到电源电压，以控制流过补偿晶体管的电流量。与补偿晶体管串联的另外的跳变点晶体管的栅极耦合到输入信号以帮助稳定跳变点。输出级反相器从输入反相器的输出提供CMOS逻辑电平。

7. 发明授权

US6011386A Frequency adjustable, zero temperature coefficient referencing ring oscillator circuit 失效
标题翻译：频率可调，零温度系数参考环形振荡器电路
公开(公告)号：US6011386A
公开(公告)日：2000-01-04
申请号：US911897
申请日：1997-08-15
申请人： Wen Li , Manny K. F. Ma
发明人： Wen Li , Manny K. F. Ma
IPC分类号： G05F3/24 , G05F3/26 , G05F3/08
CPC分类号： G05F3/262 , G05F3/242
摘要： A frequency adjustable, zero temperature coefficient referencing ring oscillator circuit includes a plurality of inverter stages each having a switching circuit that produces the oscillating output signal for the ring oscillator circuit and a control circuit that controls the switching circuit to establish the frequency of the output signal, the control circuit including field-effect transistors which are operated as output resistance controllable devices and which have their operating points, and thus their output resistances, established by a reference voltage that is produced by a precision reference voltage generating circuit so that the operating frequency of the ring oscillator circuit can be set by adjusting the value of the reference signals produced by the precision reference signal generating circuit and is maintained at the setpoint value because the precision reference voltage generating circuit operates independently of variations in temperature and/or the power supply voltage. The ring oscillator circuit is fabricated as an integrated circuit device and the operating frequency of the integrated circuit ring oscillator circuit can be adjusted after fabrication and passivation of the integrated circuit device.
摘要翻译：频率可调，零温度系数参考环形振荡器电路包括多个反相器级，每个反相器级具有产生环形振荡器电路的振荡输出信号的开关电路和控制开关电路以建立输出信号频率的控制电路所述控制电路包括作为输出电阻可控设备操作并具有其工作点的场效应晶体管，并且因此其输出电阻由由精密参考电压发生电路产生的参考电压建立，使得工作频率可以通过调整精密基准信号发生电路产生的参考信号的值来设置环形振荡器电路，并且由于精密基准电压产生电路独立于温度和/或电源的变化而运行，因此保持在设定值卷天气好环形振荡器电路被制造为集成电路器件，并且集成电路环形振荡器电路的工作频率可以在集成电路器件的制造和钝化之后被调整。

8. 发明授权

US5744839A ESD protection using selective siliciding techniques 失效
公开(公告)号：US5744839A
公开(公告)日：1998-04-28
申请号：US661447
申请日：1996-06-11
申请人： Manny K. F. Ma , Aaron Schoenfeld
发明人： Manny K. F. Ma , Aaron Schoenfeld
IPC分类号： H01L27/02 , H01L23/62
CPC分类号： H01L27/0251
摘要： The present invention relates to methods and apparatus for manufacturing semiconductor devices, and in particular for forming electrostatic discharge (ESD) protection devices, using selective siliciding, in a CMOS integrated circuit. Predetermined discharge paths are created for discharging input and output buffer pads, during an ESD event, through ESD protection devices. During fabrication, an oxide layer is utilized as a mask to prevent silicided regions from forming in source/drain regions, self-aligned with the gates. The buffer transistor gate-to-contact spacing is made longer than the gate-to-contact spacing in the associated protection transistor, to shunt charge through the protection device. In a further embodiment, active area resistance is formed between the output/input buffer transistor and the ESD protection device, to further increase the resistance of the path between the buffer pad to the associated buffer transistor.

9. 发明授权

US5578941A Voltage compensating CMOS input buffer circuit 失效
公开(公告)号：US5578941A
公开(公告)日：1996-11-26
申请号：US518546
申请日：1995-08-23
申请人： Joseph C. Sher , Manny K. F. Ma
发明人： Joseph C. Sher , Manny K. F. Ma
IPC分类号： H03K19/003 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/018521 , H03K19/00384
摘要： A voltage compensating CMOS input buffer converts input TTL signals to CMOS logic levels, and compensates for changing supply voltage by using a n-channel transistor to vary the effective size ratio of pairs p-channel to n-channel transistors making up an input inverter. The compensating transistor becomes operable with increasing supply voltage to help the n-channel input inverter transistors offset the p-channel input inverter transistors whose trip points would otherwise have been increased by increasing power supply voltage. As the power supply voltage decreases, the compensating transistor turns off, returning the input inverter to its original size ratio. The gate of the compensating transistor is coupled to the supply voltage through two diodes to control the amount of current flowing through the compensating transistor. Further trip point transistors in series with the compensating transistor have their gates coupled to the input signals to help stabilize the trip points. An output stage inverter provides the CMOS logic levels from the output of the input inverter.

10. 发明授权

US6055193A Charge pump circuits and devices containing such 有权
标题翻译：电荷泵电路和包含此类的装置
公开(公告)号：US6055193A
公开(公告)日：2000-04-25
申请号：US348808
申请日：1999-07-07
申请人： Troy A. Manning , Manny K. F. Ma
发明人： Troy A. Manning , Manny K. F. Ma
IPC分类号： G11C5/14 , G11C11/4074 , G11C7/00
CPC分类号： G11C5/146 , G11C11/4074
摘要： Circuits to convert an input voltage supply to an output voltage supply having a different magnitude or polarity. The circuits include a capacitor having a first terminal and a second terminal, a first switch coupled to the first terminal of the capacitor, and a second switch. The circuits further include a first node coupled between the second terminal of the capacitor and the second switch, and a third switch having a first terminal coupled to the first node and a second terminal coupled to a second node. The first switch is adapted to couple the first terminal of the capacitor to the input supply voltage during a fill state and a second voltage level during a dump state. The second switch is adapted to couple the first node to a third voltage level during the fill state and present a high impedance to the first node during the dump state. The third switch is adapted to dump a charge from the first node to the second node during the dump state, thereby producing an output voltage at the second node.
摘要翻译：将输入电压源转换为具有不同大小或极性的输出电压源的电路。电路包括具有第一端子和第二端子的电容器，耦合到电容器的第一端子的第一开关和第二开关。电路还包括耦合在电容器的第二端子和第二开关之间的第一节点和具有耦合到第一节点的第一端子的第三开关和耦合到第二节点的第二端子。第一开关适于在充电状态期间将电容器的第一端子耦合到输入电源电压，并且在转储状态期间将第二电压电平耦合到第二电压电平。第二开关适于在填充状态期间将第一节点耦合到第三电压电平，并且在转储状态期间向第一节点呈现高阻抗。第三开关适于在转储状态期间将电荷从第一节点转储到第二节点，从而在第二节点产生输出电压。

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