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1. 发明授权

US5924128A Pseudo zero cycle address generator and fast memory access 失效
标题翻译：伪零周期地址发生器和快速存储器访问
公开(公告)号：US5924128A
公开(公告)日：1999-07-13
申请号：US668262
申请日：1996-06-20
申请人： Dave A. Luick , Kenneth J. Kiefer , Steve R. Kunkel , Philip B. Winterfield
发明人： Dave A. Luick , Kenneth J. Kiefer , Steve R. Kunkel , Philip B. Winterfield
IPC分类号： G06F9/355 , G06F9/38 , G06F12/06
CPC分类号： G06F9/355 , G06F9/383
摘要： A method and apparatus estimate the memory address needed for a low level programming instruction in reduced instruction set computing systems. Taking advantage of a known computing environment and data architecture, bits from a displacement field in an Instruction Register may be combined with bits from a Base Register through hardware logic circuitry, preferably performing a mathematical computation such as addition. Together with bits gated directly from the Base Register and the displacement field, the combined bits form an estimate of the effective address of the desired memory location. The estimation is performed early in an instruction cycle, and therefore allows data from the memory, preferably a Data Cache, to be available at the end of the next instruction cycle, thus producing the address in what appears to be zero cycles. The method and apparatus avoid stall conditions from the CPU, and are particularly useful for Very Long Instruction Word architecture.
摘要翻译：方法和装置估计精简指令集计算系统中低级编程指令所需的存储器地址。利用已知的计算环境和数据架构，来自指令寄存器中的位移字段的位可以通过硬件逻辑电路与来自基本寄存器的位组合，优选地执行诸如加法的数学计算。与基址寄存器和位移字段直接选通的位一起，组合位形成期望存储器位置的有效地址的估计。在指令周期中早期执行估计，因此允许来自存储器，优选数据高速缓冲存储器的数据在下一个指令周期结束时可用，从而产生看起来为零周期的地址。该方法和装置避免了CPU的停顿状态，对于超长指令字架构尤其有用。

2. 发明授权

US06223208B1 Moving data in and out of processor units using idle register/storage functional units 失效
标题翻译：使用空闲寄存器/存储功能单元将数据移入和移出处理器单元
公开(公告)号：US06223208B1
公开(公告)日：2001-04-24
申请号：US08943260
申请日：1997-10-03
申请人： Kenneth J. Kiefer , David A. Luick , John Christopher Willis
发明人： Kenneth J. Kiefer , David A. Luick , John Christopher Willis
IPC分类号： G06F900
CPC分类号： G06F9/3009 , G06F9/30123 , G06F9/3851 , G06F9/462
摘要： In a computer system and a processor which has the capability to do multithreaded processor, the computer system and processor use idle register/storage functional units within the processor core to transfer the state of a thread out of the processor to memory or from memory to the processor core. The register/storage functional units are interrogated dynamically so that this transfer occurs only when the register/storage functional units are idle and not being used for normal instructions. Thus, a state may be transferred in whole if there are many cycles when the register/storage functional unit is idle or it may be transferred in part if there an insufficient number of no-op instructions for the entire state. A context switch unit in the processor then has appropriate registers and logic control to keep track of the state of the thread that is being “idly” transferred and then transfer the remaining registers when a register/storage functional is available or “idle.”
摘要翻译：在具有执行多线程处理器能力的计算机系统和处理器中，计算机系统和处理器使用处理器核心内的空闲寄存器/存储功能单元将线程的状态从处理器传送到存储器或从存储器传输到存储器处理器核心。寄存器/存储功能单元被动态询问，以便仅当寄存器/存储功能单元空闲并且不用于正常指令时才发生该转移。因此，如果在寄存器/存储功能单元空闲时存在多个周期，或者如果整个状态的无操作指令数量不足，则状态可以全部传送。然后，处理器中的上下文切换单元具有适当的寄存器和逻辑控制，以跟踪正在“空转”的线程的状态，然后当寄存器/存储功能可用或“空闲”时传送剩余的寄存器。

3. 发明授权

US6112299A Method and apparatus to select the next instruction in a superscalar or a very long instruction word computer having N-way branching 失效
标题翻译：在具有N分支的超标量或非常长的指令字计算机中选择下一条指令的方法和装置
公开(公告)号：US6112299A
公开(公告)日：2000-08-29
申请号：US001527
申请日：1997-12-31
申请人： Kemal Ebcioglu , Kenneth J. Kiefer , David Arnold Luick , Gabriel Mauricio Silberman , Philip Braun Winterfield
发明人： Kemal Ebcioglu , Kenneth J. Kiefer , David Arnold Luick , Gabriel Mauricio Silberman , Philip Braun Winterfield
IPC分类号： G06F12/08 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3814 , G06F9/30058 , G06F9/3802 , G06F9/3804 , G06F9/3842 , G06F9/3885
摘要： In a computer capable of executing a superscalar and a very long instruction word instruction wherein the computer has compiled a number of primitive operations that can be executed in parallel into a single instruction having multiple parcels and each of the parcels correspond to an operation, the invention is an improved instruction cache to store all potential subsequent instructions and a method to select the subsequent instruction when several possible branches of execution are probable and must be evaluated. All branch conditions and all addresses of potential subsequent instructions of an instruction are replicated and stored in the instruction cache. All potential subsequent instructions are stored in the same block of the instruction cache having the same next address; individual instructions are identified by the replicated offset addresses. Further the instruction cache is divided into minicaches, each minicache to store one parcel, which allows rapid autonomous execution of each parcel. Simultaneously, all branch conditions are evaluated in parallel to determine the next instruction and all offset addresses are decoded in parallel. Only after the control flow or the branch taken, or the subsequent or next instruction is determined, are the results of that branch stored and the decoded addresses are used to late select the next instruction from the instruction cache.
摘要翻译：在能够执行超标量和非常长的指令字指令的计算机中，其中计算机已经编译了可以并行执行的多个原语操作，该单个指令具有多个包裹并且每个包裹对应于一个操作，本发明是一种改进的指令高速缓存，用于存储所有可能的后续指令，以及当几个可能的执行分支是可能的并且必须被评估时选择后续指令的方法。所有分支条件和指令的潜在后续指令的所有地址被复制并存储在指令高速缓存中。所有潜在的后续指令被存储在具有相同下一个地址的指令高速缓存的相同块中; 单个指令由复制的偏移地址识别。此外，指令高速缓存分为微型存储器，每个微型存储器都存储一个包裹，这允许快速自动执行每个包裹。同时，并行评估所有分支条件，以确定下一条指令，并且所有偏移地址都被并行解码。只有在控制流程或分支获取后，或者确定后续指令或下一条指令之后，存储该分支的结果，并且解码的地址用于从指令高速缓存中晚选择下一条指令。

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