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1. 发明授权

US5924128A Pseudo zero cycle address generator and fast memory access 失效
标题翻译：伪零周期地址发生器和快速存储器访问
公开(公告)号：US5924128A
公开(公告)日：1999-07-13
申请号：US668262
申请日：1996-06-20
申请人： Dave A. Luick , Kenneth J. Kiefer , Steve R. Kunkel , Philip B. Winterfield
发明人： Dave A. Luick , Kenneth J. Kiefer , Steve R. Kunkel , Philip B. Winterfield
IPC分类号： G06F9/355 , G06F9/38 , G06F12/06
CPC分类号： G06F9/355 , G06F9/383
摘要： A method and apparatus estimate the memory address needed for a low level programming instruction in reduced instruction set computing systems. Taking advantage of a known computing environment and data architecture, bits from a displacement field in an Instruction Register may be combined with bits from a Base Register through hardware logic circuitry, preferably performing a mathematical computation such as addition. Together with bits gated directly from the Base Register and the displacement field, the combined bits form an estimate of the effective address of the desired memory location. The estimation is performed early in an instruction cycle, and therefore allows data from the memory, preferably a Data Cache, to be available at the end of the next instruction cycle, thus producing the address in what appears to be zero cycles. The method and apparatus avoid stall conditions from the CPU, and are particularly useful for Very Long Instruction Word architecture.
摘要翻译：方法和装置估计精简指令集计算系统中低级编程指令所需的存储器地址。利用已知的计算环境和数据架构，来自指令寄存器中的位移字段的位可以通过硬件逻辑电路与来自基本寄存器的位组合，优选地执行诸如加法的数学计算。与基址寄存器和位移字段直接选通的位一起，组合位形成期望存储器位置的有效地址的估计。在指令周期中早期执行估计，因此允许来自存储器，优选数据高速缓冲存储器的数据在下一个指令周期结束时可用，从而产生看起来为零周期的地址。该方法和装置避免了CPU的停顿状态，对于超长指令字架构尤其有用。

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