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1. 发明授权

US5872990A Reordering of memory reference operations and conflict resolution via rollback in a multiprocessing environment 失效
标题翻译：通过多处理环境中的回滚重新排序内存引用操作和冲突解决
公开(公告)号：US5872990A
公开(公告)日：1999-02-16
申请号：US779071
申请日：1997-01-07
申请人： David Arnold Luick , John Christopher Willis , Philip Braun Winterfield
发明人： David Arnold Luick , John Christopher Willis , Philip Braun Winterfield
IPC分类号： G06F9/38 , G06F9/45 , G06F9/46
CPC分类号： G06F9/52 , G06F8/445 , G06F9/3834 , G06F9/3863
摘要： Compile and/or run time instruction scheduling is used in a multiprocessing system to reorder memory access instructions such that a strongly consistent programming model is emulated in a fashion transparent to the programmer. The multiprocessing system detects potential shared memory conflicts, avoiding these conflicts by restarting operation of the affected processing unit at a predetermined previous state, previously archived in a rollback register set, and resuming instruction execution from that state.
摘要翻译：在多处理系统中使用编译和/或运行时指令调度来重新排序存储器访问指令，使得以对编程器透明的方式来模拟强烈一致的编程模型。多处理系统检测潜在的共享内存冲突，通过在预先存储在回滚寄存器组中的预定先前状态下重新启动受影响的处理单元的操作，以及从该状态恢复指令执行来避免这些冲突。

2. 发明授权

US06240498B1 Object oriented storage pool apparatus and method 失效
标题翻译：面向对象的存储池设备和方法
公开(公告)号：US06240498B1
公开(公告)日：2001-05-29
申请号：US09226070
申请日：1999-01-06
申请人： Steven Michael Dickes , Philip Braun Winterfield
发明人： Steven Michael Dickes , Philip Braun Winterfield
IPC分类号： G06F700
CPC分类号： G06F12/023 , Y10S707/99944
摘要： An object oriented storage pool provides enhanced performance by allowing very fast and efficient allocation of storage elements from the storage pool instead of obtaining a storage element from the heap in an object oriented computer system. The storage pool is preferably in a linked-list format, and operations on the linked list to allocate and return storage elements are atomic operations to assure serialization of accesses to the storage pool. The presence and operation of the storage pool is hidden from the user by overloading the New() and delete() methods that are defined in the programming language. In this manner the storage pool can be introduced without modification to existing application software, thereby enhancing computer system performance without changing other software in the system.
摘要翻译：面向对象的存储池通过允许从存储池非常快速和有效地分配存储元素而不是在面向对象的计算机系统中的堆中获取存储元素来提供增强的性能。存储池优选地是链表格式，并且链接列表上的分配和返回存储元件的操作是确保对存储池的访问的序列化的原子操作。通过重载编程语言中定义的New（）和delete（）方法，存储池的存在和操作将被用户隐藏。以这种方式，可以不修改现有应用软件来引入存储池，从而在不改变系统中的其他软件的情况下增强计算机系统性能。

3. 发明授权

US6112299A Method and apparatus to select the next instruction in a superscalar or a very long instruction word computer having N-way branching 失效
标题翻译：在具有N分支的超标量或非常长的指令字计算机中选择下一条指令的方法和装置
公开(公告)号：US6112299A
公开(公告)日：2000-08-29
申请号：US001527
申请日：1997-12-31
申请人： Kemal Ebcioglu , Kenneth J. Kiefer , David Arnold Luick , Gabriel Mauricio Silberman , Philip Braun Winterfield
发明人： Kemal Ebcioglu , Kenneth J. Kiefer , David Arnold Luick , Gabriel Mauricio Silberman , Philip Braun Winterfield
IPC分类号： G06F12/08 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3814 , G06F9/30058 , G06F9/3802 , G06F9/3804 , G06F9/3842 , G06F9/3885
摘要： In a computer capable of executing a superscalar and a very long instruction word instruction wherein the computer has compiled a number of primitive operations that can be executed in parallel into a single instruction having multiple parcels and each of the parcels correspond to an operation, the invention is an improved instruction cache to store all potential subsequent instructions and a method to select the subsequent instruction when several possible branches of execution are probable and must be evaluated. All branch conditions and all addresses of potential subsequent instructions of an instruction are replicated and stored in the instruction cache. All potential subsequent instructions are stored in the same block of the instruction cache having the same next address; individual instructions are identified by the replicated offset addresses. Further the instruction cache is divided into minicaches, each minicache to store one parcel, which allows rapid autonomous execution of each parcel. Simultaneously, all branch conditions are evaluated in parallel to determine the next instruction and all offset addresses are decoded in parallel. Only after the control flow or the branch taken, or the subsequent or next instruction is determined, are the results of that branch stored and the decoded addresses are used to late select the next instruction from the instruction cache.
摘要翻译：在能够执行超标量和非常长的指令字指令的计算机中，其中计算机已经编译了可以并行执行的多个原语操作，该单个指令具有多个包裹并且每个包裹对应于一个操作，本发明是一种改进的指令高速缓存，用于存储所有可能的后续指令，以及当几个可能的执行分支是可能的并且必须被评估时选择后续指令的方法。所有分支条件和指令的潜在后续指令的所有地址被复制并存储在指令高速缓存中。所有潜在的后续指令被存储在具有相同下一个地址的指令高速缓存的相同块中; 单个指令由复制的偏移地址识别。此外，指令高速缓存分为微型存储器，每个微型存储器都存储一个包裹，这允许快速自动执行每个包裹。同时，并行评估所有分支条件，以确定下一条指令，并且所有偏移地址都被并行解码。只有在控制流程或分支获取后，或者确定后续指令或下一条指令之后，存储该分支的结果，并且解码的地址用于从指令高速缓存中晚选择下一条指令。

4. 发明授权

US5734910A Integrating multi-modal synchronous interrupt handlers for computer system 失效
标题翻译：集成计算机系统的多模态同步中断处理程序
公开(公告)号：US5734910A
公开(公告)日：1998-03-31
申请号：US577831
申请日：1995-12-22
申请人： Michael Joseph Corrigan , Steven Leonard Jones , Larry Wayne Loen , David Robert Russell, Jr. , Philip Braun Winterfield
发明人： Michael Joseph Corrigan , Steven Leonard Jones , Larry Wayne Loen , David Robert Russell, Jr. , Philip Braun Winterfield
IPC分类号： G06F9/46 , G06F9/48
CPC分类号： G06F9/4812 , G06F9/463
摘要： A synchronous interrupt handler for a processing system executing multiple modes of operation employs a minimum number of lines of interrupt handler code written to execute at the "zeroth" level, is combined with a virtualized interrupt vector table. An identical zeroeth level handler is inserted at each of the processor's interrupt vector entry pints. These short code sequences are the first to gain control following an interrupt. They are handwritten in the platform's native instruction set to be mode-independent. For example, if the platform's processor does not alter the "endianness" of the machine state following an interrupt, the "zeroeth level" code must be written for endian neutrality; likewise, for 32/64-bit mode, etc. For each mode of operation, there is created a Virtualized Vector Table to represent the proper interrupt handlers for each physical interrupt level. Each task data structure, implicitly reflecting its unique mode of operation, contains a pointer to its virtualized vector table. The zeroeth-level handlers then extract the virtualized vector table reference for their own interrupt level and indirectly pass control to the preloaded table value.
摘要翻译：执行多种操作模式的处理系统的同步中断处理程序使用写入“第零”级执行的最少数量的中断处理程序代码与虚拟中断向量表组合。每个处理器的中断向量入口品位都插入相同的零级处理器。这些短代码序列是在中断之后首先获得控制的。它们在平台的本机指令集中手写成与模式无关。例如，如果平台的处理器不会在中断之后改变机器状态的“字节顺序”，则必须为端点中立写入“零级”代码; 同样，对于+ E，fra 32/64 + EE位模式等。对于每种操作模式，都创建了一个虚拟化向量表来表示每个物理中断级别的适当的中断处理程序。每个任务数据结构，隐含地反映其唯一的操作模式，包含一个指向其虚拟向量表的指针。零级处理程序然后提取虚拟化向量表引用自己的中断级别，并将控制间接地传递给预加载的表值。

5. 发明授权

US6088769A Multiprocessor cache coherence directed by combined local and global tables 失效
标题翻译：由局部和全局表组合引导的多处理器缓存一致性
公开(公告)号：US6088769A
公开(公告)日：2000-07-11
申请号：US724628
申请日：1996-10-01
申请人： David Arnold Luick , John Christopher Willis , Philip Braun Winterfield
发明人： David Arnold Luick , John Christopher Willis , Philip Braun Winterfield
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/082 , G06F12/0826
摘要： A method and apparatus for maintaining coherence between shared data stored within a plurality of memory devices, each memory device residing in a different node within a tightly coupled multiprocessor system. Each node includes a "local coherence unit" and an associated processor. A cache unit is associated with each memory/processor pair. Each local coherence unit maintains a table which indicates whether the most current copy of data stored within the node resides in the local memory, in the local cache, or in a non-local cache. The present invention includes a "global coherence" unit coupled to each node via the logical interconnect. The global coherence unit includes a interconnect monitoring device and a global coherence table. When data which resides within the memory of a first node is transferred to a second node, the interconnect monitoring device updates the global coherence table to indicate that the data is being shared. The global coherence table also preferably indicates in which node a copy of the most current data resides.
摘要翻译：一种用于维持存储在多个存储设备中的共享数据之间的一致性的方法和装置，每个存储器设备驻留在紧密耦合的多处理器系统内的不同节点中。每个节点包括“局部相干单元”和相关联的处理器。高速缓存单元与每个存储器/处理器对相关联。每个局部相干单元维护表，该表指示存储在节点内的最新数据副本是否驻留在本地存储器，本地高速缓存中或非本地高速缓存中。本发明包括通过逻辑互连耦合到每个节点的“全局相干”单元。全局相干单元包括互连监视设备和全局相干表。当驻留在第一节点的存储器内的数据被传送到第二节点时，互连监视设备更新全局一致性表以指示正在共享数据。全局一致性表还优选地指示哪个节点存在最新数据的副本。

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