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1. 发明授权

US08268667B2 Memory device using ion implant isolated conductive metal oxide 有权
标题翻译：使用离子注入隔离导电金属氧化物的存储器件
公开(公告)号：US08268667B2
公开(公告)日：2012-09-18
申请号：US13215895
申请日：2011-08-23
申请人： Darrell Rinerson , Robin Cheung , David Hansen , Steven Longcor , Rene Meyer , Jonathan Bornstein , Lawrence Schloss
发明人： Darrell Rinerson , Robin Cheung , David Hansen , Steven Longcor , Rene Meyer , Jonathan Bornstein , Lawrence Schloss
IPC分类号： H01L21/00
CPC分类号： F01D17/26 , F04D29/563 , H01L21/02565 , H01L27/0688 , H01L27/2409 , H01L27/2418 , H01L27/2472 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1666
摘要： Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).
摘要翻译：公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOx，LaSrCoOx，LaNiOx等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触并且形成用于将非易失性数据存储为多个的存储元件（例如，表示存储数据的电阻状态）。

2. 发明申请

US20100159641A1 Memory cell formation using ion implant isolated conductive metal oxide 失效
标题翻译：使用离子注入隔离导电金属氧化物的存储单元形成
公开(公告)号：US20100159641A1
公开(公告)日：2010-06-24
申请号：US12653851
申请日：2009-12-18
申请人： Darrell Rinerson , Jonathan Bornstein , David Hansen , Robin Cheung , Steven W. Longcor , Rene Meyer , Lawrence Schloss
发明人： Darrell Rinerson , Jonathan Bornstein , David Hansen , Robin Cheung , Steven W. Longcor , Rene Meyer , Lawrence Schloss
IPC分类号： H01L21/34
CPC分类号： F01D17/26 , F04D29/563 , H01L21/02565 , H01L27/0688 , H01L27/2409 , H01L27/2418 , H01L27/2472 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1666
摘要： Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).
摘要翻译：公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOX，LaSrCoOX，LaNiOX等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触，并且形成用于将非易失性数据存储为多个的存储元件（例如，表示存储数据的电阻状态）。

3. 发明授权

US08003511B2 Memory cell formation using ion implant isolated conductive metal oxide 失效
标题翻译：使用离子注入隔离导电金属氧化物的存储单元形成
公开(公告)号：US08003511B2
公开(公告)日：2011-08-23
申请号：US12653851
申请日：2009-12-18
申请人： Darrell Rinerson , Jonathan Bornstein , Robin Cheung , David Hansen , Steven W. Longcor , Rene Meyer , Lawrence Schloss
发明人： Darrell Rinerson , Jonathan Bornstein , Robin Cheung , David Hansen , Steven W. Longcor , Rene Meyer , Lawrence Schloss
IPC分类号： H01L21/44
CPC分类号： F01D17/26 , F04D29/563 , H01L21/02565 , H01L27/0688 , H01L27/2409 , H01L27/2418 , H01L27/2472 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1666
摘要： Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).
摘要翻译：公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOX，LaSrCoOX，LaNiOX等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触，并且形成用于将非易失性数据存储为多个的存储元件（例如，表示存储数据的电阻状态）。

4. 发明申请

US20060171200A1 Memory using mixed valence conductive oxides 审中-公开
标题翻译：使用混合价态导电氧化物的记忆
公开(公告)号：US20060171200A1
公开(公告)日：2006-08-03
申请号：US11095026
申请日：2005-03-30
申请人： Darrell Rinerson , Christophe Chevallier , Wayne Kinney , Roy Lambertson , Steven Longcor , John Sanchez , Lawrence Schloss , Philip Swab , Edmond Ward
发明人： Darrell Rinerson , Christophe Chevallier , Wayne Kinney , Roy Lambertson , Steven Longcor , John Sanchez , Lawrence Schloss , Philip Swab , Edmond Ward
IPC分类号： G11C11/34
CPC分类号： H01L45/08 , G06F17/5045 , G11C11/5685 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/005 , G11C2013/009 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/54 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1625
摘要： A memory using a mixed valence conductive oxides. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
摘要翻译：使用混合价态导电氧化物的记忆。存储器包括在其缺氧状态下导电性较差的混合价态导电氧化物和作为电解质的氧的混合电子离子导体并且促进有效引起氧离子运动的电场。

5. 发明申请

US20060158998A1 Movable terminal in a two terminal memory array 失效
标题翻译：两个终端存储器阵列中的可移动终端
公开(公告)号：US20060158998A1
公开(公告)日：2006-07-20
申请号：US11037971
申请日：2005-01-18
申请人： Darrell Rinerson , Christophe Chevallier , John Sanchez , Lawrence Schloss
发明人： Darrell Rinerson , Christophe Chevallier , John Sanchez , Lawrence Schloss
IPC分类号： G11B9/00
CPC分类号： G11B9/08 , B82Y10/00 , G11B9/1445
摘要： A movable terminal in a two terminal memory array. A storage medium is disposed between two terminals, one of the terminals being movable relative to the second terminal. Either one of the terminals or both terminals might actually move, resulting in one terminal being moved relative to the other terminal. A memory element disposed between the two terminals has a conductance that is responsive to a write voltage across the electrodes.
摘要翻译：二端存储器阵列中的可动端子。存储介质设置在两个端子之间，其中一个端子可相对于第二端子移动。终端或两个终端中的任一个可能实际上移动，导致一个终端相对于另一个终端移动。设置在两个端子之间的存储元件具有响应电极两端的写入电压的电导。

6. 发明授权

US08395928B2 Threshold device for a memory array 有权
公开(公告)号：US08395928B2
公开(公告)日：2013-03-12
申请号：US13206460
申请日：2011-08-09
申请人： Julie Casperson Brewer , Christophe Chevallier , Wayne Kinney , Roy Lambertson , Darrell Rinerson , Lawrence Schloss
发明人： Julie Casperson Brewer , Christophe Chevallier , Wayne Kinney , Roy Lambertson , Darrell Rinerson , Lawrence Schloss
IPC分类号： G11C11/36
CPC分类号： G11C7/02 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/71 , G11C2213/76 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/147
摘要： A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.

7. 发明申请

US20090303772A1 Two-Terminal Reversibly Switchable Memory Device 审中-公开
标题翻译：双端可逆切换存储器
公开(公告)号：US20090303772A1
公开(公告)日：2009-12-10
申请号：US12456627
申请日：2009-06-18
申请人： Darrell Rinerson , Christophe Chevallier , Wayne Kinney , Roy Lambertson , John E. Sanchez, JR. , Lawrence Schloss , Philip Swab , Edmond Ward
发明人： Darrell Rinerson , Christophe Chevallier , Wayne Kinney , Roy Lambertson , John E. Sanchez, JR. , Lawrence Schloss , Philip Swab , Edmond Ward
IPC分类号： G11C11/00 , H01L45/00 , G11C7/00
CPC分类号： H01L45/08 , G06F17/5045 , G11C11/5685 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/005 , G11C2013/009 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/54 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1625
摘要： A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
摘要翻译：公开了使用混合价态导电氧化物的记忆体。存储器包括在其缺氧状态下导电性较差的混合价态导电氧化物和作为电解质的氧的混合电子离子导体并且促进有效引起氧离子运动的电场。

8. 发明申请

US20090027976A1 Threshold device for a memory array 失效
标题翻译：内存阵列的阈值设备
公开(公告)号：US20090027976A1
公开(公告)日：2009-01-29
申请号：US11881473
申请日：2007-07-26
申请人： Julie Casperson Brewer , Darrell Rinerson , Christophe J. Chevallier , Wayne Kinney , Roy Lambertson , Lawrence Schloss
发明人： Julie Casperson Brewer , Darrell Rinerson , Christophe J. Chevallier , Wayne Kinney , Roy Lambertson , Lawrence Schloss
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/71 , G11C2213/76 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/147
摘要： A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.
摘要翻译：公开了一种阈值装置，其包括彼此接触并且由多种不同介电材料制成的多个相邻隧道势垒层。具有第一和第二端子的存储器插头包括与第一和第二端子串联的阈值装置和存储数据作为多个导电率曲线的存储元件。阈值装置可操作以在数据操作期间根据施加的电压施加限定通过存储元件的电流的特征I-V曲线。阈值装置基本上减少或消除了通过半选择或未选择的存储器插头的电流，并且允许足够大的电流流过被选择用于读取和写入操作的存储器插头。阈值器件减少或消除半选择的存储器插头中的数据干扰，并在读取操作期间增加S / N比。

9. 发明授权

US07995371B2 Threshold device for a memory array 失效
标题翻译：内存阵列的阈值设备
公开(公告)号：US07995371B2
公开(公告)日：2011-08-09
申请号：US11881473
申请日：2007-07-26
申请人： Darrell Rinerson , Julie Casperson Brewer , Christophe J. Chevallier , Wayne Kinney , Roy Lambertson , Lawrence Schloss
发明人： Darrell Rinerson , Julie Casperson Brewer , Christophe J. Chevallier , Wayne Kinney , Roy Lambertson , Lawrence Schloss
IPC分类号： G11C11/00
CPC分类号： G11C7/02 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/71 , G11C2213/76 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/147
摘要： A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.
摘要翻译：公开了一种阈值装置，其包括彼此接触并且由多种不同介电材料制成的多个相邻隧道势垒层。具有第一和第二端子的存储器插头包括与第一和第二端子串联的阈值装置和存储数据作为多个导电率曲线的存储元件。阈值装置可操作以在数据操作期间根据施加的电压施加限定通过存储元件的电流的特征I-V曲线。阈值装置基本上减少或消除了通过半选择或未选择的存储器插头的电流，并且允许足够大的电流流过被选择用于读取和写入操作的存储器插头。阈值器件减少或消除半选择的存储器插头中的数据干扰，并在读取操作期间增加S / N比。

10. 发明授权

US08320161B2 Conductive metal oxide structures in non volatile re writable memory devices 有权
标题翻译：非易失性可重写存储器件中的导电金属氧化物结构
公开(公告)号：US08320161B2
公开(公告)日：2012-11-27
申请号：US13252932
申请日：2011-10-04
申请人： Lawrence Schloss , Julie Casperson Brewer , Wayne Kinney , Rene Meyer
发明人： Lawrence Schloss , Julie Casperson Brewer , Wayne Kinney , Rene Meyer
IPC分类号： G11C11/21
CPC分类号： H01L45/085 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C2013/0073 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76
摘要： A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).
摘要翻译：公开了包括与导电金属氧化物（CMO）接触的电解绝缘体的存储元件的存储单元。 CMO包括晶体结构并且可以包含烧绿石氧化物，导电二元氧化物，多个B位钙钛矿和Ruddlesden-Popper结构。 CMO包括可以响应于施加在电解绝缘体和CMO上施加的写入电压产生的适当幅度和方向的电场，可以将其输送到电解绝缘体/从电解绝缘体传输的移动离子。存储器单元可以包括与存储元件电串联的非欧姆器件（NOD）。存储器单元可以位于单层存储器中的两端交叉点存储器阵列中的导电阵列线的交叉点或多个垂直堆叠的存储器层之间，该衬底层在衬底上制造，该衬底包括用于数据的有源电路对数组层进行操作。

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