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1. 发明授权

US08003511B2 Memory cell formation using ion implant isolated conductive metal oxide 失效
标题翻译：使用离子注入隔离导电金属氧化物的存储单元形成
公开(公告)号：US08003511B2
公开(公告)日：2011-08-23
申请号：US12653851
申请日：2009-12-18
申请人： Darrell Rinerson , Jonathan Bornstein , Robin Cheung , David Hansen , Steven W. Longcor , Rene Meyer , Lawrence Schloss
发明人： Darrell Rinerson , Jonathan Bornstein , Robin Cheung , David Hansen , Steven W. Longcor , Rene Meyer , Lawrence Schloss
IPC分类号： H01L21/44
CPC分类号： F01D17/26 , F04D29/563 , H01L21/02565 , H01L27/0688 , H01L27/2409 , H01L27/2418 , H01L27/2472 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1666
摘要： Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).
摘要翻译：公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOX，LaSrCoOX，LaNiOX等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触，并且形成用于将非易失性数据存储为多个的存储元件（例如，表示存储数据的电阻状态）。

2. 发明申请

US20100159641A1 Memory cell formation using ion implant isolated conductive metal oxide 失效
标题翻译：使用离子注入隔离导电金属氧化物的存储单元形成
公开(公告)号：US20100159641A1
公开(公告)日：2010-06-24
申请号：US12653851
申请日：2009-12-18
申请人： Darrell Rinerson , Jonathan Bornstein , David Hansen , Robin Cheung , Steven W. Longcor , Rene Meyer , Lawrence Schloss
发明人： Darrell Rinerson , Jonathan Bornstein , David Hansen , Robin Cheung , Steven W. Longcor , Rene Meyer , Lawrence Schloss
IPC分类号： H01L21/34
CPC分类号： F01D17/26 , F04D29/563 , H01L21/02565 , H01L27/0688 , H01L27/2409 , H01L27/2418 , H01L27/2472 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1666
摘要： Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).
摘要翻译：公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOX，LaSrCoOX，LaNiOX等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触，并且形成用于将非易失性数据存储为多个的存储元件（例如，表示存储数据的电阻状态）。

3. 发明申请

US20110204019A1 Method of making a planar electrode 审中-公开
标题翻译：制作平面电极的方法
公开(公告)号：US20110204019A1
公开(公告)日：2011-08-25
申请号：US12927552
申请日：2010-11-15
申请人： Jonathan Bornstein , David Hansen , Steven W. Longcor
发明人： Jonathan Bornstein , David Hansen , Steven W. Longcor
IPC分类号： H05K3/00
摘要： Chemical mechanical polishing (CMP) of thin film materials using a slurry including a surfactant chemical operative to polish high portions of the film being planarized while preventing the polishing of low portions of the film is disclosed. The low portions can be in a step reduction region of a deposited film. The CMP process can be used for form a planar surface upon which subsequent thin-film layers can be deposited, such as an electrically conductive material for an electrode. The subsequently deposited thin-film layers are substantially planar as deposited without having to use CMP. The resulting thin-film layers are planar and have a uniform cross-sectional thickness that can be beneficial for layers of memory material for a memory cell. The processing can be performed back-end-of-the-line (BEOL) on a previously front-end-of-the-line (FEOL) processed substrate (e.g., silicon wafer) and the BEOL process can be used to fabricate two-terminal non-volatile cross-point memory arrays.
摘要翻译：公开了使用包括表面活性剂化学品的浆料的薄膜材料的化学机械抛光（CMP），其可操作以抛光待平坦化的膜的高部分，同时防止薄膜的低部分的抛光。低部分可以在沉积膜的阶梯还原区域中。 CMP工艺可以用于形成平坦表面，在该平面上可以沉积后续的薄膜层，例如用于电极的导电材料。随后沉积的薄膜层基本上是平面的，不必使用CMP沉积。所得到的薄膜层是平面的并且具有均匀的横截面厚度，这对存储单元的记忆材料层是有利的。可以在先前的前端（FEOL）处理的基板（例如，硅晶片）上执行后端处理（BEOL），并且BEOL过程可用于制造两个 - 终端非易失性交叉点存储器阵列。

4. 发明授权

US07832090B1 Method of making a planar electrode 失效
标题翻译：制作平面电极的方法
公开(公告)号：US07832090B1
公开(公告)日：2010-11-16
申请号：US12660424
申请日：2010-02-25
申请人： Jonathan Bornstein , David Hansen , Steven W. Longcor
发明人： Jonathan Bornstein , David Hansen , Steven W. Longcor
IPC分类号： H01R43/00
CPC分类号： H01L27/24 , H01L21/3212 , H01L21/7684 , H01L21/76849 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165
摘要： Chemical mechanical polishing (CMP) of thin film materials using a slurry including a surfactant chemical operative to polish high portions of the film being planarized while preventing the polishing of low portions of the film is disclosed. The low portions can be in a step reduction region of a deposited film. The CMP process can be used for form a planar surface upon which subsequent thin-film layers can be deposited, such as an electrically conductive material for an electrode. The subsequently deposited thin-film layers are substantially planar as deposited without having to use CMP. The resulting thin-film layers are planar and have a uniform cross-sectional thickness that can be beneficial for layers of memory material for a memory cell. The processing can be performed back-end-of-the-line (BEOL) on a previously front-end-of-the-line (FEOL) processed substrate (e.g., silicon wafer) and the BEOL process can be used to fabricate two-terminal non-volatile cross-point memory arrays.
摘要翻译：公开了使用包括表面活性剂化学品的浆料的薄膜材料的化学机械抛光（CMP），其可操作以抛光待平坦化的膜的高部分，同时防止薄膜的低部分的抛光。低部分可以在沉积膜的阶梯还原区域中。 CMP工艺可以用于形成平坦表面，在该平面上可以沉积后续的薄膜层，例如用于电极的导电材料。随后沉积的薄膜层基本上是平面的，不必使用CMP沉积。所得到的薄膜层是平面的并且具有均匀的横截面厚度，这对存储单元的记忆材料层是有利的。可以在先前的前端（FEOL）处理的基板（例如，硅晶片）上执行后端处理（BEOL），并且BEOL过程可用于制造两个 - 终端非易失性交叉点存储器阵列。

5. 发明授权

US07889539B2 Multi-resistive state memory device with conductive oxide electrodes 有权
公开(公告)号：US07889539B2
公开(公告)日：2011-02-15
申请号：US12653486
申请日：2009-12-14
申请人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
发明人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
IPC分类号： G11C11/00 , H01L49/00
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.

6. 发明申请

US20100157657A1 Multi-resistive state memory device with conductive oxide electrodes 有权
标题翻译：具有导电氧化物电极的多电阻状态存储器件
公开(公告)号：US20100157657A1
公开(公告)日：2010-06-24
申请号：US12653486
申请日：2009-12-14
申请人： Darrell Rinerson , Wayne Kinney , Edmond R. Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe J. Chevallier , John Sanchez , Philip F.S. Swab
发明人： Darrell Rinerson , Wayne Kinney , Edmond R. Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe J. Chevallier , John Sanchez , Philip F.S. Swab
IPC分类号： G11C11/00
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
摘要翻译：公开了一种包括导电氧化物电极的存储单元。存储单元包括用于将数据存储为多个电阻状态的存储元件。存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。导电氧化物层也可以与金属层（例如Pt）接触。存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。

7. 发明申请

US20090016094A1 Selection device for Re-Writable memory 有权
标题翻译：可重写存储器的选择装置
公开(公告)号：US20090016094A1
公开(公告)日：2009-01-15
申请号：US12283339
申请日：2008-09-11
申请人： Darrell Rinerson , Steve Kuo-Ren Hsia , Steven W. Longcor , Wayne Kinney , Edmond B. Ward , Christophe J. Chevallier
发明人： Darrell Rinerson , Steve Kuo-Ren Hsia , Steven W. Longcor , Wayne Kinney , Edmond B. Ward , Christophe J. Chevallier
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C11/00 , G11C11/56 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/77 , G11C2213/79 , H01L27/11502 , H01L27/11507 , H01L27/24 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/00 , H01L45/10 , H01L45/1233 , H01L45/147
摘要： A memory cell including a memory element and a non-ohmic device (NOD) that are electrically in series with each other is disclosed. The NOD comprises a semiconductor based selection device operative to electrically isolate the memory element from a range of voltages applied across the memory cell that are not read voltages operative read stored data from the memory element or write voltages operative to write data to the memory element. The selection device may comprise a pair of diodes that are electrically in series with each other and disposed in a back-to-back configuration. The memory cell may be fabricated over a substrate (e.g., a silicon wafer) that includes active circuitry. The selection device and the semiconductor materials (e.g., poly-silicon) that form the selection device are fabricated above the substrate and are integrated with other thin film layers of material that form the memory cell.
摘要翻译：公开了一种包括彼此电串联的存储元件和非欧姆器件（NOD）的存储单元。 NOD包括基于半导体的选择装置，其操作以将存储器元件与施加在存储器单元上的电压范围电隔离，所述电压范围不是读取电压，从存储元件读取存储的数据，或者写入电压可操作以将数据写入存储器元件。选择装置可以包括彼此电连接并以背对背配置设置的一对二极管。可以在包括有源电路的衬底（例如，硅晶片）上制造存储器单元。形成选择装置的选择装置和半导体材料（例如，多晶硅）制造在衬底之上，并与形成存储单元的材料的其它薄膜层集成。

8. 发明申请

US20080293196A1 Method for fabricating multi-resistive state memory devices 有权
标题翻译：制造多电阻状态存储器件的方法
公开(公告)号：US20080293196A1
公开(公告)日：2008-11-27
申请号：US12215958
申请日：2008-06-30
申请人： Darrell Rinerson , Wayne Kinney , Edmond R. Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe J. Chevallier , John Sanchez , Philip F.S. Swab
发明人： Darrell Rinerson , Wayne Kinney , Edmond R. Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe J. Chevallier , John Sanchez , Philip F.S. Swab
IPC分类号： H01L21/8244
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
摘要翻译：提供经处理的导电元件。可以通过在导电元件上沉积反应性金属或非常薄的材料层来处理导电元件。反应性金属（或非常薄的材料层）通常将夹在导电元件和电极之间。该结构还具有非线性IV特性，这在某些阵列中是有利的。

9. 发明授权

US07180772B2 High-density NVRAM 有权
标题翻译：高密度NVRAM
公开(公告)号：US07180772B2
公开(公告)日：2007-02-20
申请号：US11179790
申请日：2005-07-11
申请人： Darrell Rinerson , Steven W. Longcor , Edmond R. Ward , Wayne Kinney
发明人： Darrell Rinerson , Steven W. Longcor , Edmond R. Ward , Wayne Kinney
IPC分类号： G11C11/14
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/71 , G11C2213/77
摘要： A cross point array and peripheral circuitry that accesses the cross point array. The peripheral circuitry receives a supply voltage of approximately 1.8 volts or less, generates voltages of a magnitude not more than approximately 3 volts, and senses current that is indicative of a nonvolatile memory state.
摘要翻译：交叉点阵列和访问交叉点阵列的外围电路。外围电路接收大约1.8伏或更小的电源电压，产生不大于约3伏的电压，并且感测指示非易失性存储器状态的电流。

10. 发明授权

US07067862B2 Conductive memory device with conductive oxide electrodes 失效
标题翻译：具有导电氧化物电极的导电存储器件
公开(公告)号：US07067862B2
公开(公告)日：2006-06-27
申请号：US10682277
申请日：2003-10-08
申请人： Darrell Rinerson , Steven W. Longcor , Steve Kuo-Ren Hsia , Wayne Kinney , Edmond R. Ward , Christophe J. Chevallier
发明人： Darrell Rinerson , Steven W. Longcor , Steve Kuo-Ren Hsia , Wayne Kinney , Edmond R. Ward , Christophe J. Chevallier
IPC分类号： H01L31/062
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/003 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/77 , H01L27/24 , H01L27/2418 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/165
摘要： A multi-resistive state element that uses barrier electrodes is provided. If certain materials are used as electrodes, the electrodes can be used for multiple purposes. Oxides and nitrides are especially well suited for acting as a barrier layer, and possibly even an adhesion layer and a sacrificial layer.
摘要翻译：提供了使用阻挡电极的多电阻状态元件。如果使用某些材料作为电极，电极可用于多种用途。氧化物和氮化物特别适用于作为阻挡层，甚至可能甚至粘附层和牺牲层。

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