专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06822909B1 Method of controlling program threshold voltage distribution of a dual cell memory device 有权
标题翻译：控制双电池存储器件的程序阈值电压分布的方法
公开(公告)号：US06822909B1
公开(公告)日：2004-11-23
申请号：US10422090
申请日：2003-04-24
申请人： Darlene G. Hamilton , Edward Hsia , Mark W. Randolph , Edward F. Runnion , Kulachet Tanpairoj
发明人： Darlene G. Hamilton , Edward Hsia , Mark W. Randolph , Edward F. Runnion , Kulachet Tanpairoj
IPC分类号： G11C1134
CPC分类号： G11C16/0475 , G11C11/5671 , G11C16/3454
摘要： A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. The method can include applying an initial program pulse to the memory device; comparing the threshold voltage of the memory device with a verify threshold voltage; and if the threshold voltage of the memory device is less than the verify threshold voltage, applying a second program pulse to the memory device during which at least one condition of the second program pulse is modified from the initial program pulse.
摘要翻译：一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。该方法可以包括将初始编程脉冲施加到存储器件; 将存储器件的阈值电压与验证阈值电压进行比较; 并且如果所述存储器件的阈值电压小于所述验证阈值电压，则向所述存储器件施加第二编程脉冲，在所述存储器件期间，从所述初始编程脉冲修改所述第二编程脉冲的至少一个条件。

2. 发明授权

US06775187B1 Method of programming a dual cell memory device 失效
标题翻译：编程双单元存储器件的方法
公开(公告)号：US06775187B1
公开(公告)日：2004-08-10
申请号：US10422489
申请日：2003-04-24
申请人： Darlene G. Hamilton , Edward F. Runnion , Edward Hsia , Kulachet Tanpairoj
发明人： Darlene G. Hamilton , Edward F. Runnion , Edward Hsia , Kulachet Tanpairoj
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0475
摘要： A method of programming a dual cell memory device having a first charge storing cell and second charge storing cell. The first charge storing cell can be pre-read to determine if the first charge storing cell stores an amount of charge to increase a threshold voltage of the memory device over a specified threshold voltage. If not, the second charge storing cell can be programmed with a standard program pulse. If so, the second charge storing cell can be programed with a modified program pulse.
摘要翻译：一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。可以预先读取第一电荷存储单元，以确定第一电荷存储单元是否存储一定量的电荷以增加存储器件的阈值电压超过指定的阈值电压。如果不是，则可以用标准编程脉冲编程第二电荷存储单元。如果是这样，则可以用修改的编程脉冲对第二电荷存储单元进行编程。

3. 发明授权

US06967873B2 Memory device and method using positive gate stress to recover overerased cell 有权
公开(公告)号：US06967873B2
公开(公告)日：2005-11-22
申请号：US10677790
申请日：2003-10-02
申请人： Darlene G. Hamilton , Zhizheng Liu , Mark W. Randolph , Yi He , Edward Hsia , Kulachet Tanpairoj , Mimi Lee , Alykhan Madhani
发明人： Darlene G. Hamilton , Zhizheng Liu , Mark W. Randolph , Yi He , Edward Hsia , Kulachet Tanpairoj , Mimi Lee , Alykhan Madhani
IPC分类号： G11C16/04 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3404 , G11C16/0475 , G11C16/107 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345
摘要： A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.

4. 发明授权

US06813752B1 Method of determining charge loss activation energy of a memory array 失效
标题翻译：确定存储器阵列的电荷损耗激活能的方法
公开(公告)号：US06813752B1
公开(公告)日：2004-11-02
申请号：US10306667
申请日：2002-11-26
申请人： Edward Hsia , Darlene G. Hamilton , Wei Zheng , Mark W. Randolph , Kulachet Tanpairoj
发明人： Edward Hsia , Darlene G. Hamilton , Wei Zheng , Mark W. Randolph , Kulachet Tanpairoj
IPC分类号： G06F1750
CPC分类号： G11C29/50 , G11C16/04
摘要： A method of determining charge loss activation for a memory array. Memory arrays are programmed with a pattern for testing charge loss. Then, respective bake times are calculated for the memory arrays to experience a given amount of charge loss at their respective bake temperatures. Then, charge loss activation energy is calculated, based on the respective bake times. In one version, the memory arrays are cycled by repeatedly erasing and reprogramming them before baking. In another embodiment, various regions of the memory arrays are programmed to a plurality of distinct delta threshold voltages before baking.
摘要翻译：确定存储器阵列的电荷损失激活的方法。存储器阵列被编程用于测试电荷损失的模式。然后，对于存储器阵列计算各自的烘烤时间，以在其各自的烘烤温度下经历给定量的电荷损失。然后，基于相应的烘烤时间计算电荷损失激活能。在一个版本中，通过在烘烤之前重复擦除和重新编程它们来循环存储器阵列。在另一个实施例中，存储器阵列的各个区域在烘烤之前被编程为多个不同的增量阈值电压。

5. 发明授权

US06956768B2 Method of programming dual cell memory device to store multiple data states per cell 有权
标题翻译：编程双单元存储器件以存储每个单元的多个数据状态的方法
公开(公告)号：US06956768B2
公开(公告)日：2005-10-18
申请号：US10413800
申请日：2003-04-15
申请人： Darlene G. Hamilton , Kulachet Tanpairoj , Edward Hsia , Yi He
发明人： Darlene G. Hamilton , Kulachet Tanpairoj , Edward Hsia , Yi He
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/10
摘要： A method of programming a multi-level, dual cell memory device. The method includes independently programming a first charge storing cell and a second charge storing cell to respective data states, the data states selected from a blank program level or one of a plurality of charged program levels. Also disclosed is a method of reading the multi-level, dual cell memory device using a plurality of reference currents.
摘要翻译：一种编程多级双电池存储器件的方法。该方法包括将第一电荷存储单元和第二电荷存储单元独立地编程为相应的数据状态，从空白程序级或多个带电程序级中的一个选择的数据状态。还公开了一种使用多个参考电流读取多电平双电池存储器件的方法。

6. 发明授权

US06778442B1 Method of dual cell memory device operation for improved end-of-life read margin 有权
标题翻译：双电池存储器件操作方法，用于改善寿命终止读取余量
公开(公告)号：US06778442B1
公开(公告)日：2004-08-17
申请号：US10422092
申请日：2003-04-24
申请人： Darlene G. Hamilton , Edward Hsia , Kulachet Tanpairoj , Alykhan Madhani , Mimi Lee
发明人： Darlene G. Hamilton , Edward Hsia , Kulachet Tanpairoj , Alykhan Madhani , Mimi Lee
IPC分类号： G11C1134
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/3418 , G11C16/3454
摘要： A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. According to one aspect of the method, the method can include over-erasing the first and second charge storing cells to shift an erase state threshold voltage of the memory device to be lower than a natural state threshold voltage. According to another aspect of the method, the method can include programming the first and second charge storing cells to the same data state and verifying that the second programmed charge storing cell stores charge corresponding to the data state. If the verification fails, both charge storing cells can be re-pulsed.
摘要翻译：一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。根据该方法的一个方面，该方法可以包括过度擦除第一和第二电荷存储单元，以使存储器件的擦除状态阈值电压低于自然状态阈值电压。根据该方法的另一方面，该方法可以包括将第一和第二电荷存储单元编程为相同的数据状态，并验证第二编程电荷存储单元存储对应于数据状态的电荷。如果验证失败，则电荷存储单元可以被重新脉冲。

7. 发明授权

US06735114B1 Method of improving dynamic reference tracking for flash memory unit 有权
标题翻译：改进闪存单元动态参考跟踪的方法
公开(公告)号：US06735114B1
公开(公告)日：2004-05-11
申请号：US10357879
申请日：2003-02-04
申请人： Darlene G. Hamilton , Eric M. Ajimine , Ming-Huei Shieh , Lee Cleveland , Edward F. Runnion , Mark W. Randolph , Sameer S. Haddad
发明人： Darlene G. Hamilton , Eric M. Ajimine , Ming-Huei Shieh , Lee Cleveland , Edward F. Runnion , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C1604
CPC分类号： G11C16/3418 , G11C16/0475 , G11C16/28
摘要： A method of programming a memory unit having a plurality of dual cell core memory devices and at least one dual cell dynamic reference device. The memory unit is subjected to an erase configuration operation such that each cell of the core memory devices is in a blank state and such that a threshold voltage of the at least one dynamic reference device is less than a charged program level threshold voltage. Thereafter, the at least one dynamic reference and the core memory devices are programmed using a page programming routine.
摘要翻译：一种编程具有多个双单元核心存储器件和至少一个双单元动态参考器件的存储器单元的方法。对存储器单元进行擦除配置操作，使得核心存储器件的每个单元处于空白状态，并且使得至少一个动态参考器件的阈值电压小于充电的程序电平阈值电压。此后，使用页面编程例程对至少一个动态参考和核心存储器设备进行编程。

8. 发明授权

US06788583B2 Pre-charge method for reading a non-volatile memory cell 失效
标题翻译：用于读取非易失性存储单元的预充电方法
公开(公告)号：US06788583B2
公开(公告)日：2004-09-07
申请号：US10307749
申请日：2002-12-02
申请人： Yi He , Edward F. Runnion , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Pauling Chen , Binh Le
发明人： Yi He , Edward F. Runnion , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Pauling Chen , Binh Le
IPC分类号： G11C1606
CPC分类号： G11C7/12 , G11C16/0475 , G11C16/24
摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.
摘要翻译：一种检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括使与第一存储单元的沟道区形成源极结的第一位线接地。高电压被施加到第一存储单元的栅极和第二位线，第二位线是第一位线右侧的下一个位线，并且仅与通道区域从第一位线分离。位于第二位线右侧的下一个位线的第三位线是隔离的，使得其电位仅由其与第二通道区域的结和仅在第三位的相对侧上的第三通道区域线。将高电压施加到位于第三位线右侧的预充电位线，并且在第二位线处检测电流以确定存储器单元的源位的编程状态。

9. 发明授权

US06771545B1 Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array 有权
标题翻译：用于读取与非易失性存储单元阵列的非活动区域相邻的非易失性存储单元的方法
公开(公告)号：US06771545B1
公开(公告)日：2004-08-03
申请号：US10353558
申请日：2003-01-29
申请人： Edward Hsia , Eric Ajimine , Darlene G. Hamilton , Pauling Chen , Ming-Huei Shieh , Mark W. Randolph , Edward Runnion , Yi He
发明人： Edward Hsia , Eric Ajimine , Darlene G. Hamilton , Pauling Chen , Ming-Huei Shieh , Mark W. Randolph , Edward Runnion , Yi He
IPC分类号： G11C1604
CPC分类号： G11C29/82 , G11C16/0491 , G11C16/3404
摘要： An array of non-volatile memory cells includes active columns of cells wherein a data pattern may be stored adjacent to damaged or inactive columns wherein data is not stored. A method of storing a data pattern and reproducing the data pattern within such an array comprises storing a charge within a selected plurality of the memory cells within the active column. The selected plurality of memory cells represents a portion of the data pattern. An inactive memory cell programming pattern is identified. The inactive memory cell programming pattern identifies all, or a selected plurality, of the memory cells in the inactive column in which a charge is to be stored for the purpose of periodically storing a charge in the memory cells first inactive column to prevent over erasure, during bulk erase, and leakage from the inactive cells to adjacent active cells. A charge is stored on the selected plurality of the memory cells in the first inactive column. The data pattern is reproduced reading each memory cell within the first active column.
摘要翻译：非易失性存储器单元的阵列包括有效的单元格列，其中数据模式可以存储在与不存储数据的损坏或非活动列相邻的位置。存储数据模式并在其中再现数据模式的方法包括将电荷存储在活动列内的所选择的多个存储单元内。所选择的多个存储单元表示数据模式的一部分。识别非活动存储器单元编程模式。非活动存储器单元编程模式识别要在其中存储电荷的所述非活动列中的所有或选定的多个存储单元，以便在存储单元的第一非活动列中周期性地存储电荷以防止过度擦除，在批量擦除期间以及从非活性电池泄漏到相邻的活性电池。在第一非活动列中的所选择的多个存储器单元上存储电荷。读取在第一活动列内的每个存储单元的数据模式。

10. 发明授权

US06590811B1 Higher program VT and faster programming rates based on improved erase methods 失效
公开(公告)号：US06590811B1
公开(公告)日：2003-07-08
申请号：US10173262
申请日：2002-06-17
申请人： Darlene G. Hamilton , Narbeh Derhacobian , Janet S. Y. Wang , Kulachet Tanpairoj
发明人： Darlene G. Hamilton , Narbeh Derhacobian , Janet S. Y. Wang , Kulachet Tanpairoj
IPC分类号： G11C1134
CPC分类号： G11C16/3409 , G11C11/5671 , G11C16/04 , G11C16/0475 , G11C16/10 , G11C16/3404 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/50 , G11C29/50004
摘要： A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming, programming times are kept short without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles. The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式