专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07250334B2 Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode 有权
标题翻译：金属绝缘体金属（MIM）电容器制造与侧壁间隔和铝帽（ALCAP）顶部电极
公开(公告)号：US07250334B2
公开(公告)日：2007-07-31
申请号：US10909648
申请日：2004-07-31
申请人： Darius L. Crenshaw , Byron L. Williams , Alwin Tsao , Hisashi Shichijo , Satyavolu S. Papa Rao , Kenneth D. Brennan , Steven A. Lytle
发明人： Darius L. Crenshaw , Byron L. Williams , Alwin Tsao , Hisashi Shichijo , Satyavolu S. Papa Rao , Kenneth D. Brennan , Steven A. Lytle
IPC分类号： H01L21/8242
CPC分类号： H01L23/5223 , H01L21/76834 , H01L28/57 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.
摘要翻译：公开了形成MIM（金属绝缘金属）电容器的方法（10），其中即使电容器按比例缩小，也减轻了与铜扩散相关的不利影响。侧壁间隔物（156）抵靠着底部电极/铜扩散阻挡材料层（136）的边缘（137），电容器介电材料层（150）的边缘（151）和至少一些边缘（153）的顶层电极材料层。侧壁间隔物（156）是电介质或非导电的，并且减轻由于铜扩散而在板之间产生的“短路”电流。底部电极扩散阻挡材料（136）减轻了铜扩散和/或铜漂移，从而降低了设备过早失效的可能性。

2. 发明授权

US5100827A Buried antifuse 失效
标题翻译：埋地反熔丝
公开(公告)号：US5100827A
公开(公告)日：1992-03-31
申请号：US661736
申请日：1991-02-27
申请人： Steven A. Lytle
发明人： Steven A. Lytle
IPC分类号： H01L21/82 , H01L21/768 , H01L21/822 , H01L23/522 , H01L23/525 , H01L27/04
CPC分类号： H01L23/5252 , H01L21/76888 , H01L2924/0002 , Y10S148/055
摘要： An integrated circuit having one or more antifuses which connect electrical components through a dielectric layer. The antifuse is formed before the thick dielectric is deposited and patterned to form windows which expose the antifuse.

3. 发明申请

US20090102501A1 TEST STRUCTURES FOR E-BEAM TESTING OF SYSTEMATIC AND RANDOM DEFECTS IN INTEGRATED CIRCUITS 审中-公开
标题翻译：集成电路中系统和随机缺陷的电子束测试的测试结构
公开(公告)号：US20090102501A1
公开(公告)日：2009-04-23
申请号：US11875185
申请日：2007-10-19
申请人： Richard L. Guldi , Toan Tran , Deepak Ramappa , Steven A. Lytle
发明人： Richard L. Guldi , Toan Tran , Deepak Ramappa , Steven A. Lytle
IPC分类号： G01N23/225 , G01R31/26
CPC分类号： G01R31/2884 , G01R31/307 , H01L22/14 , H01L22/34
摘要： In accordance with the invention, there are electron beam inspection systems, electron beam testable semiconductor test structures, and methods for detecting systematic defects, such as, for example contact-to-gate shorts, worm hole leakage paths, holes printing issues, and anomalies in sparse holes and random defects, such as, current leakage paths due to dislocations and pipes during semiconductor processing.
摘要翻译：根据本发明，存在电子束检查系统，电子束可测试半导体测试结构和用于检测系统缺陷的方法，例如接触到栅极短路，蠕虫孔泄漏路径，孔打印问题和异常稀疏孔和随机缺陷，例如在半导体处理期间由于位错和管道引起的电流泄漏路径。

4. 发明授权

US06218085B1 Process for photoresist rework to avoid sodium incorporation 失效
标题翻译：光刻胶返修工艺，避免钠掺入
公开(公告)号：US06218085B1
公开(公告)日：2001-04-17
申请号：US09400406
申请日：1999-09-21
申请人： Simon J. Molloy , Nace Layadi , Allen Yen , Brian D. Crevasse , Steven A. Lytle
发明人： Simon J. Molloy , Nace Layadi , Allen Yen , Brian D. Crevasse , Steven A. Lytle
IPC分类号： G03F736
CPC分类号： G03F7/427
摘要： A method for stripping photoresist material (26) from a semiconductor substrate (16) avoids incorporation of sodium and other contaminant ions from a rework solvent. An oxygen and hydrogen plasma mixture strips the photoresist material without significant introduction of oxygen into the titanium nitride layer (24). Any oxidation of the titanium nitride is reversed by exposing the substrate to an oxygen-free, reducing plasma, such as a hydrogen-containing plasma. The titanium nitride layer is thereby much less susceptible to incorporation of contaminant ions in a subsequent cleaning with rework solvent than a layer which has been extensively oxidized during the plasma stripping process.
摘要翻译：用于从半导体衬底（16）剥离光致抗蚀剂材料（26）的方法避免了从返工溶剂中引入钠和其它污染物离子。氧和氢等离子体混合物剥离光致抗蚀剂材料，而不会在氧化钛层（24）内显着引入氧气。通过将衬底暴露于无氧还原等离子体（例如含氢等离子体）中，氮化钛的任何氧化反转。因此，氮化钛层比在等离子体剥离过程中已经被广泛氧化的层更难于掺杂污染物离子以进行随后的返工溶剂清洗。

5. 发明授权

US06989602B1 Dual damascene process with no passing metal features 有权
标题翻译：双镶嵌工艺，没有通过金属特征
公开(公告)号：US06989602B1
公开(公告)日：2006-01-24
申请号：US09667046
申请日：2000-09-21
申请人： Steven A. Lytle
发明人： Steven A. Lytle
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76808 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of forming integrated circuit interconnect structures wherein a passing metal feature does not include a landing pad. In an exemplary embodiment, the method includes forming a via opening through first and second dielectric layers, such as silicon dioxide layer, located over a conductive layer, such as copper, and to a first etch stop layer, such as silicon nitride, located over the conductive layer. A trench opening is then formed through the second dielectric layer and to a second etch stop layer. Once the via and trench openings are formed, an etch is conducted that etches through the first etch stop layer such that the opening contacts the underlying conductive layer.
摘要翻译：本发明提供一种形成集成电路互连结构的方法，其中通过的金属特征不包括着陆焊盘。在一个示例性实施例中，该方法包括通过位于诸如铜的导电层之上的第一和第二电介质层（例如二氧化硅层）形成通孔，以及位于上方的第一蚀刻停止层（例如氮化硅）导电层。然后通过第二介电层和第二蚀刻停止层形成沟槽开口。一旦形成通孔和沟槽开口，就进行蚀刻通过第一蚀刻停止层的蚀刻，使得开口接触下面的导电层。

6. 发明授权

US06555910B1 Use of small openings in large topography features to improve dielectric thickness control and a method of manufacture thereof 有权
标题翻译：在大地形特征中使用小开口以改善电介质厚度控制及其制造方法
公开(公告)号：US06555910B1
公开(公告)日：2003-04-29
申请号：US09651661
申请日：2000-08-29
申请人： Robert A. Ashton , Steven A. Lytle , Mary D. Roby , Morgan J. Thoma , Daniel J. Vitkavage
发明人： Robert A. Ashton , Steven A. Lytle , Mary D. Roby , Morgan J. Thoma , Daniel J. Vitkavage
IPC分类号： H01L2348
CPC分类号： H01L21/02112 , H01L21/02274 , H01L21/02304 , H01L21/31051 , H01L21/31629 , H01L21/76819 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device and method of manufacture thereof that provides improved dielectric thickness control. The semiconductor device includes a metal feature located on a semiconductor substrate, wherein the metal feature has openings formed therein, or depending on the device, therethrough. The semiconductor device further includes a fluorinated dielectric layer located over the metal feature and within the openings. Thus, the inclusion of openings within the metal feature allows for a substantially planar surface of the fluorinated dielectric layer.
摘要翻译：本发明提供了一种提供改进的电介质厚度控制的半导体器件及其制造方法。半导体器件包括位于半导体衬底上的金属特征，其中金属特征具有形成于其中的取决于器件的开口。半导体器件还包括位于金属特征上方且位于开口内的氟化电介质层。因此，在金属特征内包含开口允许氟化电介质层的基本平坦的表面。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式