专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07703085B2 Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms 有权
标题翻译：将高级编程语言程序转换为混合计算平台的统一可执行程序
公开(公告)号：US07703085B2
公开(公告)日：2010-04-20
申请号：US11243498
申请日：2005-10-04
申请人： Daniel Poznanovic , Jeffrey Hammes , Lisa Krause , Jon Steidel , David Barker , Jeffrey Paul Brooks
发明人： Daniel Poznanovic , Jeffrey Hammes , Lisa Krause , Jon Steidel , David Barker , Jeffrey Paul Brooks
IPC分类号： G06F9/45 , G00O9/44
CPC分类号： G06F17/5045 , G06F8/447
摘要： A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation. The driver invokes a hardware description language (HDL) compiler to produce a netlist file that can be used to start the place-and-route compilation needed to produce a bitstream for the reconfigurable computer. The programming environment then provides support for taking the output from the compilation driver and combining all the necessary components together to produce a unified executable capable of running on both the instruction processor and reconfigurable processor.
摘要翻译：一种用于编译写入以符合高级语言标准的计算机代码的系统和方法，以生成包含用于可重构处理器的硬件逻辑的统一可执行程序，用于传统处理器（指令处理器）的指令以及用于管理的相关支持代码在混合硬件平台上执行。不需要明确的编写硬件级设计代码的知识，因为问题可以用高级语言语法表示。顶级驱动程序调用符合标准的编译器，提供句法和语义分析。驱动程序调用编译阶段，将生成的CFG表示转换为混合控制流数据流图表示，表示可被处理为硬件描述表示的优化流水线逻辑。驱动程序调用硬件描述语言（HDL）编译器来产生一个网表文件，该文件可用于启动可重配置计算机生成比特流所需的布局和路由编译。然后，编程环境提供了从编译驱动器获取输出并将所有必要组件组合在一起以产生能够在指令处理器和可重配置处理器上运行的统一可执行文件的支持。

2. 发明授权

US06983456B2 Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms 有权
标题翻译：将高级编程语言程序转换为混合计算平台的统一可执行程序
公开(公告)号：US06983456B2
公开(公告)日：2006-01-03
申请号：US10285299
申请日：2002-10-31
申请人： Daniel Poznanovic , Jeffrey Hammes , Lisa Krause , Jon Steidel , David Barker , Jeffrey Paul Brooks
发明人： Daniel Poznanovic , Jeffrey Hammes , Lisa Krause , Jon Steidel , David Barker , Jeffrey Paul Brooks
IPC分类号： G06F9/44
CPC分类号： G06F17/5045 , G06F8/447
摘要： A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation. The driver invokes a hardware description language (HDL) compiler to produce a netlist file that can be used to start the place-and-route compilation needed to produce a bitstream for the reconfigurable computer. The programming environment then provides support for taking the output from the compilation driver and combining all the necessary components together to produce a unified executable capable of running on both the instruction processor and reconfigurable processor.
摘要翻译：一种用于编译写入以符合高级语言标准的计算机代码的系统和方法，以生成包含用于可重构处理器的硬件逻辑的统一可执行程序，用于传统处理器（指令处理器）的指令以及用于管理的相关支持代码在混合硬件平台上执行。不需要明确的编写硬件级设计代码的知识，因为问题可以用高级语言语法表示。顶级驱动程序调用符合标准的编译器，提供句法和语义分析。驱动程序调用编译阶段，将生成的CFG表示转换为混合控制流数据流图表示，表示可被处理为硬件描述表示的优化流水线逻辑。驱动程序调用硬件描述语言（HDL）编译器来产生一个网表文件，该文件可用于启动可重配置计算机生成比特流所需的布局和路由编译。然后，编程环境提供了从编译驱动器获取输出并将所有必要组件组合在一起以产生能够在指令处理器和可重配置处理器上运行的统一可执行文件的支持。

3. 发明申请

US20060041872A1 Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms 有权
公开(公告)号：US20060041872A1
公开(公告)日：2006-02-23
申请号：US11243498
申请日：2005-10-04
申请人： Daniel Poznanovic , Jeffrey Hammes , Lisa Krause , Jon Steidel , David Barker , Jeffrey Brooks
发明人： Daniel Poznanovic , Jeffrey Hammes , Lisa Krause , Jon Steidel , David Barker , Jeffrey Brooks
IPC分类号： G06F9/45
CPC分类号： G06F17/5045 , G06F8/447
摘要： A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation. The driver invokes a hardware description language (HDL) compiler to produce a netlist file that can be used to start the place-and-route compilation needed to produce a bitstream for the reconfigurable computer. The programming environment then provides support for taking the output from the compilation driver and combining all the necessary components together to produce a unified executable capable of running on both the instruction processor and reconfigurable processor.

4. 发明授权

US06964029B2 System and method for partitioning control-dataflow graph representations 有权
标题翻译：用于分区控制数据流图表示的系统和方法
公开(公告)号：US06964029B2
公开(公告)日：2005-11-08
申请号：US10285298
申请日：2002-10-31
申请人： Daniel Poznanovic , Jeffrey Hammes , Lisa Krause , Jon Steidel
发明人： Daniel Poznanovic , Jeffrey Hammes , Lisa Krause , Jon Steidel
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： An embodiment of the invention includes a system for partitioning a control-flow graph representation into a reconfigurable portion and an instruction processor portion. Another embodiment of the invention includes a method of partitioning a control-dataflow graph representation that includes dividing the control-dataflow graph into two or more partition blocks, comparing the estimated performance of at least one of the partition blocks as reconfigurable logic versus instruction processor code; and assigning said at least one of the partition blocks to reconfigurable hardware or an instruction processor based on said comparing step.
摘要翻译：本发明的实施例包括用于将控制流图表示划分成可重配置部分和指令处理器部分的系统。本发明的另一个实施例包括一种对控制数据流图表示进行分区的方法，该方法包括将控制数据流图划分成两个或更多个分区块，将至少一个分区块的估计性能作为可重构逻辑与指令处理器代码进行比较 ; 以及基于所述比较步骤，将所述分区块中的所述至少一个分配给可重配置硬件或指令处理器。

5. 发明授权

US07149867B2 System and method of enhancing efficiency and utilization of memory bandwidth in reconfigurable hardware 有权
标题翻译：提高可重构硬件内存带宽的效率和利用率的系统和方法
公开(公告)号：US07149867B2
公开(公告)日：2006-12-12
申请号：US10869200
申请日：2004-06-16
申请人： Daniel Poznanovic , David E. Caliga , Jeffrey Hammes
发明人： Daniel Poznanovic , David E. Caliga , Jeffrey Hammes
IPC分类号： G06F12/00
CPC分类号： G06F9/3455 , G06F9/383 , G06F12/0862 , G06F15/7846 , G06F2212/601 , G06F2212/6026 , G06F2212/6028
摘要： A reconfigurable processor that includes a computational unit and a data prefetch unit coupled to the computational unit, where the data prefetch unit retrieves data from a memory and supplies the data to the computational unit through memory and a data access unit, and where the data prefetch unit, memory, and data access unit is configured by a program. Also, a reconfigurable hardware system that includes a common memory; and one or more reconfigurable processors coupled to the common memory, where at least one of the reconfigurable processors includes a data prefetch unit to read and write data between the unit and the common memory, and where the data prefetch unit is configured by a program executed on the system. In addition, a method of transferring data that includes transferring data between a memory and a data prefetch unit in a reconfigurable processor; and transferring the data between a computational unit and the data prefetch unit.
摘要翻译：一种可重构处理器，其包括耦合到计算单元的计算单元和数据预取单元，其中数据预取单元从存储器检索数据，并通过存储器和数据存取单元将数据提供给计算单元，并且其中数据预取单元，存储器和数据访问单元由程序配置。而且，包括公共存储器的可重新配置的硬件系统; 以及耦合到公共存储器的一个或多个可重配置处理器，其中至少一个可重构处理器包括用于在单元和公共存储器之间读取和写入数据的数据预取单元，并且其中数据预取单元由执行的程序配置在系统上另外，一种传输数据的方法，包括在可重构处理器中的存储器和数据预取单元之间传送数据; 以及在计算单元和数据预取单元之间传送数据。

6. 发明授权

US07155708B2 Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation 有权
标题翻译：使用可重构硬件仿真的控制数据流图表示调试和性能分析
公开(公告)号：US07155708B2
公开(公告)日：2006-12-26
申请号：US10285389
申请日：2002-10-31
申请人： Jeffrey Hammes , Daniel Poznanovic , Lonnie Gliem
发明人： Jeffrey Hammes , Daniel Poznanovic , Lonnie Gliem
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F17/5022
摘要： An embodiment of the invention includes a method of simulating a hybrid instruction processor and reconfigurable processor implemented algorithm which utilizes a runtime selectable emulation library that emulates a reconfigurable processor and its resources, and a control-data flow emulator that emulates the reconfigurable logic for the algorithm. Another embodiment of the invention includes a method of simulating a control-dataflow graph that includes building an internal representation of the control-dataflow graph that includes one or more dataflow code blocks, and simulating the control-dataflow graph as a sequence of code block dataflow executions, where control is passed from one code block to another code block based on the output value of the code block until EXIT is reached.
摘要翻译：本发明的实施例包括一种模拟混合指令处理器和可重构处理器实现的算法的方法，该算法利用模拟可重构处理器及其资源的运行时可选仿真库，以及模拟该算法的可重构逻辑的控制数据流仿真器。本发明的另一实施例包括一种模拟控制数据流图的方法，该方法包括构建包括一个或多个数据流代码块的控制数据流图的内部表示，以及将该控制数据流图模拟为代码块数据流序列执行，其中基于代码块的输出值，直到达到EXIT，控制从一个代码块传递到另一代码块。

7. 发明授权

US07134120B2 Map compiler pipelined loop structure 有权
标题翻译：地图编译流水线循环结构
公开(公告)号：US07134120B2
公开(公告)日：2006-11-07
申请号：US10345082
申请日：2003-01-14
申请人： Jeffrey Hammes
发明人： Jeffrey Hammes
IPC分类号： G06F9/45
CPC分类号： G06F17/5045 , G06F8/447
摘要： A control-flow dataflow graph pipelined loop structure that includes a loop body that processes an input value to generate an output value in successive iterations of the loop body, where the output value is captured by a circulate node coupled to the loop body, a loop valid node coupled to the loop body that determines a final loop iteration, and an output value storage node coupled to the circulate node, where the output value storage node ignores output values generated after the loop valid node determines the final loop iteration has occurred. Also, a control-flow dataflow graph pipelined loop structure that includes a loop body that processes an input value to generate an output value in successive iterations of the loop body, where the output value is captured by a circulate node coupled to the loop body, and a loop driver node coupled to the circulate node, where the loop driver node sets a period for each iteration of the loop body.
摘要翻译：控制流数据流图流水线循环结构，其包括循环体，其处理输入值以在循环体的连续迭代中生成输出值，其中输出值由耦合到环体的循环节点捕获，循环耦合到循环体的有效节点，其确定最终循环迭代，以及耦合到循环节点的输出值存储节点，其中输出值存储节点忽略在循环有效节点确定最终循环迭代之后生成的输出值。而且，控制流数据流图流水线循环结构，其包括循环体，其处理输入值以在循环体的连续迭代中生成输出值，其中输出值由耦合到循环体的循环节点捕获，以及耦合到循环节点的循环驱动器节点，其中循环驱动器节点设置循环体的每次迭代的周期。

8. 发明申请

US20080010444A1 ELIMINATION OF STREAM CONSUMER LOOP OVERSHOOT EFFECTS 有权
标题翻译：消除消费者环路海洋的影响
公开(公告)号：US20080010444A1
公开(公告)日：2008-01-10
申请号：US11456466
申请日：2006-07-10
申请人： Jeffrey Hammes
发明人： Jeffrey Hammes
IPC分类号： G06F9/44
CPC分类号： G06F9/3863 , G06F8/433 , G06F8/456 , G06F9/325 , G06F9/383 , G06F9/3832 , G06F9/3842
摘要： A reconfigurable processor invoking data stream pipelining is configured to associate a restore buffer with each incoming data stream. The buffer is configured to be of sufficient size to maintain data values dispatched to a loop so as to restore values fetched and lost due to loop overshoots. The restore buffer stores the values that were recently fetched from the buffer to the loop. To determine how many data values should be restored, the loop counts the number of the data values it takes from each data stream and the number of valid loop iterations that take place. Once a loop termination is detected, the loop halts the fetching of values from the restore buffer and compares, for each stream, the number of loop iterations with the number of values fetched. The difference is the number of extra values that were taken from the restore buffer and are restored.
摘要翻译：调用数据流流水线的可重配置处理器被配置为将还原缓冲器与每个输入数据流相关联。将缓冲区配置为具有足够的大小以将数据值分派到循环，以便恢复由于循环过冲而获取和丢失的值。还原缓冲区将最近从缓冲区中取出的值存储到循环中。要确定应该还原多少数据值，循环计算从每个数据流获取的数据值的数量以及发生的有效循环迭代次数。一旦检测到环路终止，循环将停止从还原缓冲区中获取值，并将每个流中的循环迭代次数与获取的值的数目进行比较。不同之处在于从恢复缓冲区中获取的额外值，并被还原。

9. 发明授权

US08589666B2 Elimination of stream consumer loop overshoot effects 有权
标题翻译：消除流消费者环路过冲效应
公开(公告)号：US08589666B2
公开(公告)日：2013-11-19
申请号：US11456466
申请日：2006-07-10
申请人： Jeffrey Hammes
发明人： Jeffrey Hammes
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3863 , G06F8/433 , G06F8/456 , G06F9/325 , G06F9/383 , G06F9/3832 , G06F9/3842
摘要： A reconfigurable processor invoking data stream pipelining is configured to associate a restore buffer with each incoming data stream. The buffer is configured to be of sufficient size to maintain data values dispatched to a loop so as to restore values fetched and lost due to loop overshoots. The restore buffer stores the values that were recently fetched from the buffer to the loop. To determine how many data values should be restored, the loop counts the number of the data values it takes from each data stream and the number of valid loop iterations that take place. Once a loop termination is detected, the loop halts the fetching of values from the restore buffer and compares, for each stream, the number of loop iterations with the number of values fetched. The difference is the number of extra values that were taken from the restore buffer and are restored.
摘要翻译：调用数据流流水线的可重配置处理器被配置为将还原缓冲器与每个输入数据流相关联。将缓冲区配置为具有足够的大小以将数据值分派到循环，以便恢复由于循环过冲而获取和丢失的值。还原缓冲区将最近从缓冲区中取出的值存储到循环中。要确定应该还原多少数据值，循环计算从每个数据流获取的数据值的数量以及发生的有效循环迭代次数。一旦检测到环路终止，循环将停止从还原缓冲区中获取值，并将每个流中的循环迭代次数与获取的值的数目进行比较。不同之处在于从恢复缓冲区中获取的额外值，并被还原。

10. 发明申请

US20130157639A1 MOBILE ELECTRONIC DEVICES UTILIZING RECONFIGURABLE PROCESSING TECHNIQUES TO ENABLE HIGHER SPEED APPLICATIONS WITH LOWERED POWER CONSUMPTION 审中-公开
标题翻译：移动电子设备利用可重构处理技术实现更低功耗的高速应用
公开(公告)号：US20130157639A1
公开(公告)日：2013-06-20
申请号：US13365090
申请日：2012-02-02
申请人： Jon M. Huppenthal , Thomas R. Seeman , Jeffrey Hammes , D. James Guzy
发明人： Jon M. Huppenthal , Thomas R. Seeman , Jeffrey Hammes , D. James Guzy
IPC分类号： H04W4/00
CPC分类号： G06F1/3234 , G06F17/5054 , G06F2217/78 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： Disclosed herein are mobile electronic devices utilizing reconfigurable processing techniques to enable higher speed applications with lowered power consumption for, inter alia, increased device battery life. The techniques disclosed herein enable greatly enhanced compression/decompression as well as encryption and decryption functionality to be provided in addition to overall greater processing capability particularly in those applications wherein minimization of power consumption is desired. Package-on-package and other assembly techniques may be used to provide the reconfigurable processor in a small footprint package.
摘要翻译：本文公开了使用可重构处理技术的移动电子设备，以便特别是增加设备电池寿命来实现具有降低的功率消耗的更高速度应用。除了总体更大的处理能力之外，本文公开的技术能够大大增强压缩/解压缩以及加密和解密功能，特别是在需要最小化功耗的那些应用中。封装封装和其他装配技术可用于以小尺寸封装提供可重构处理器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式