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    • 1. 发明授权
    • Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation
    • 使用可重构硬件仿真的控制数据流图表示调试和性能分析
    • US07155708B2
    • 2006-12-26
    • US10285389
    • 2002-10-31
    • Jeffrey HammesDaniel PoznanovicLonnie Gliem
    • Jeffrey HammesDaniel PoznanovicLonnie Gliem
    • G06F9/45G06F9/44
    • G06F17/5022
    • An embodiment of the invention includes a method of simulating a hybrid instruction processor and reconfigurable processor implemented algorithm which utilizes a runtime selectable emulation library that emulates a reconfigurable processor and its resources, and a control-data flow emulator that emulates the reconfigurable logic for the algorithm. Another embodiment of the invention includes a method of simulating a control-dataflow graph that includes building an internal representation of the control-dataflow graph that includes one or more dataflow code blocks, and simulating the control-dataflow graph as a sequence of code block dataflow executions, where control is passed from one code block to another code block based on the output value of the code block until EXIT is reached.
    • 本发明的实施例包括一种模拟混合指令处理器和可重构处理器实现的算法的方法,该算法利用模拟可重构处理器及其资源的运行时可选仿真库,以及模拟该算法的可重构逻辑的控制数据流仿真器 。 本发明的另一实施例包括一种模拟控制数据流图的方法,该方法包括构建包括一个或多个数据流代码块的控制数据流图的内部表示,以及将该控制数据流图模拟为代码块数据流序列 执行,其中基于代码块的输出值,直到达到EXIT,控制从一个代码块传递到另一代码块。