专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06964029B2 System and method for partitioning control-dataflow graph representations 有权
标题翻译：用于分区控制数据流图表示的系统和方法
公开(公告)号：US06964029B2
公开(公告)日：2005-11-08
申请号：US10285298
申请日：2002-10-31
申请人： Daniel Poznanovic , Jeffrey Hammes , Lisa Krause , Jon Steidel
发明人： Daniel Poznanovic , Jeffrey Hammes , Lisa Krause , Jon Steidel
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： An embodiment of the invention includes a system for partitioning a control-flow graph representation into a reconfigurable portion and an instruction processor portion. Another embodiment of the invention includes a method of partitioning a control-dataflow graph representation that includes dividing the control-dataflow graph into two or more partition blocks, comparing the estimated performance of at least one of the partition blocks as reconfigurable logic versus instruction processor code; and assigning said at least one of the partition blocks to reconfigurable hardware or an instruction processor based on said comparing step.
摘要翻译：本发明的实施例包括用于将控制流图表示划分成可重配置部分和指令处理器部分的系统。本发明的另一个实施例包括一种对控制数据流图表示进行分区的方法，该方法包括将控制数据流图划分成两个或更多个分区块，将至少一个分区块的估计性能作为可重构逻辑与指令处理器代码进行比较 ; 以及基于所述比较步骤，将所述分区块中的所述至少一个分配给可重配置硬件或指令处理器。

2. 发明授权

US07703085B2 Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms 有权
标题翻译：将高级编程语言程序转换为混合计算平台的统一可执行程序
公开(公告)号：US07703085B2
公开(公告)日：2010-04-20
申请号：US11243498
申请日：2005-10-04
申请人： Daniel Poznanovic , Jeffrey Hammes , Lisa Krause , Jon Steidel , David Barker , Jeffrey Paul Brooks
发明人： Daniel Poznanovic , Jeffrey Hammes , Lisa Krause , Jon Steidel , David Barker , Jeffrey Paul Brooks
IPC分类号： G06F9/45 , G00O9/44
CPC分类号： G06F17/5045 , G06F8/447
摘要： A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation. The driver invokes a hardware description language (HDL) compiler to produce a netlist file that can be used to start the place-and-route compilation needed to produce a bitstream for the reconfigurable computer. The programming environment then provides support for taking the output from the compilation driver and combining all the necessary components together to produce a unified executable capable of running on both the instruction processor and reconfigurable processor.
摘要翻译：一种用于编译写入以符合高级语言标准的计算机代码的系统和方法，以生成包含用于可重构处理器的硬件逻辑的统一可执行程序，用于传统处理器（指令处理器）的指令以及用于管理的相关支持代码在混合硬件平台上执行。不需要明确的编写硬件级设计代码的知识，因为问题可以用高级语言语法表示。顶级驱动程序调用符合标准的编译器，提供句法和语义分析。驱动程序调用编译阶段，将生成的CFG表示转换为混合控制流数据流图表示，表示可被处理为硬件描述表示的优化流水线逻辑。驱动程序调用硬件描述语言（HDL）编译器来产生一个网表文件，该文件可用于启动可重配置计算机生成比特流所需的布局和路由编译。然后，编程环境提供了从编译驱动器获取输出并将所有必要组件组合在一起以产生能够在指令处理器和可重配置处理器上运行的统一可执行文件的支持。

3. 发明授权

US06983456B2 Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms 有权
标题翻译：将高级编程语言程序转换为混合计算平台的统一可执行程序
公开(公告)号：US06983456B2
公开(公告)日：2006-01-03
申请号：US10285299
申请日：2002-10-31
申请人： Daniel Poznanovic , Jeffrey Hammes , Lisa Krause , Jon Steidel , David Barker , Jeffrey Paul Brooks
发明人： Daniel Poznanovic , Jeffrey Hammes , Lisa Krause , Jon Steidel , David Barker , Jeffrey Paul Brooks
IPC分类号： G06F9/44
CPC分类号： G06F17/5045 , G06F8/447
摘要： A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation. The driver invokes a hardware description language (HDL) compiler to produce a netlist file that can be used to start the place-and-route compilation needed to produce a bitstream for the reconfigurable computer. The programming environment then provides support for taking the output from the compilation driver and combining all the necessary components together to produce a unified executable capable of running on both the instruction processor and reconfigurable processor.
摘要翻译：一种用于编译写入以符合高级语言标准的计算机代码的系统和方法，以生成包含用于可重构处理器的硬件逻辑的统一可执行程序，用于传统处理器（指令处理器）的指令以及用于管理的相关支持代码在混合硬件平台上执行。不需要明确的编写硬件级设计代码的知识，因为问题可以用高级语言语法表示。顶级驱动程序调用符合标准的编译器，提供句法和语义分析。驱动程序调用编译阶段，将生成的CFG表示转换为混合控制流数据流图表示，表示可被处理为硬件描述表示的优化流水线逻辑。驱动程序调用硬件描述语言（HDL）编译器来产生一个网表文件，该文件可用于启动可重配置计算机生成比特流所需的布局和路由编译。然后，编程环境提供了从编译驱动器获取输出并将所有必要组件组合在一起以产生能够在指令处理器和可重配置处理器上运行的统一可执行文件的支持。

4. 发明申请

US20060041872A1 Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms 有权
公开(公告)号：US20060041872A1
公开(公告)日：2006-02-23
申请号：US11243498
申请日：2005-10-04
申请人： Daniel Poznanovic , Jeffrey Hammes , Lisa Krause , Jon Steidel , David Barker , Jeffrey Brooks
发明人： Daniel Poznanovic , Jeffrey Hammes , Lisa Krause , Jon Steidel , David Barker , Jeffrey Brooks
IPC分类号： G06F9/45
CPC分类号： G06F17/5045 , G06F8/447
摘要： A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation. The driver invokes a hardware description language (HDL) compiler to produce a netlist file that can be used to start the place-and-route compilation needed to produce a bitstream for the reconfigurable computer. The programming environment then provides support for taking the output from the compilation driver and combining all the necessary components together to produce a unified executable capable of running on both the instruction processor and reconfigurable processor.

5. 发明授权

US07149867B2 System and method of enhancing efficiency and utilization of memory bandwidth in reconfigurable hardware 有权
标题翻译：提高可重构硬件内存带宽的效率和利用率的系统和方法
公开(公告)号：US07149867B2
公开(公告)日：2006-12-12
申请号：US10869200
申请日：2004-06-16
申请人： Daniel Poznanovic , David E. Caliga , Jeffrey Hammes
发明人： Daniel Poznanovic , David E. Caliga , Jeffrey Hammes
IPC分类号： G06F12/00
CPC分类号： G06F9/3455 , G06F9/383 , G06F12/0862 , G06F15/7846 , G06F2212/601 , G06F2212/6026 , G06F2212/6028
摘要： A reconfigurable processor that includes a computational unit and a data prefetch unit coupled to the computational unit, where the data prefetch unit retrieves data from a memory and supplies the data to the computational unit through memory and a data access unit, and where the data prefetch unit, memory, and data access unit is configured by a program. Also, a reconfigurable hardware system that includes a common memory; and one or more reconfigurable processors coupled to the common memory, where at least one of the reconfigurable processors includes a data prefetch unit to read and write data between the unit and the common memory, and where the data prefetch unit is configured by a program executed on the system. In addition, a method of transferring data that includes transferring data between a memory and a data prefetch unit in a reconfigurable processor; and transferring the data between a computational unit and the data prefetch unit.
摘要翻译：一种可重构处理器，其包括耦合到计算单元的计算单元和数据预取单元，其中数据预取单元从存储器检索数据，并通过存储器和数据存取单元将数据提供给计算单元，并且其中数据预取单元，存储器和数据访问单元由程序配置。而且，包括公共存储器的可重新配置的硬件系统; 以及耦合到公共存储器的一个或多个可重配置处理器，其中至少一个可重构处理器包括用于在单元和公共存储器之间读取和写入数据的数据预取单元，并且其中数据预取单元由执行的程序配置在系统上另外，一种传输数据的方法，包括在可重构处理器中的存储器和数据预取单元之间传送数据; 以及在计算单元和数据预取单元之间传送数据。

6. 发明授权

US07155708B2 Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation 有权
标题翻译：使用可重构硬件仿真的控制数据流图表示调试和性能分析
公开(公告)号：US07155708B2
公开(公告)日：2006-12-26
申请号：US10285389
申请日：2002-10-31
申请人： Jeffrey Hammes , Daniel Poznanovic , Lonnie Gliem
发明人： Jeffrey Hammes , Daniel Poznanovic , Lonnie Gliem
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F17/5022
摘要： An embodiment of the invention includes a method of simulating a hybrid instruction processor and reconfigurable processor implemented algorithm which utilizes a runtime selectable emulation library that emulates a reconfigurable processor and its resources, and a control-data flow emulator that emulates the reconfigurable logic for the algorithm. Another embodiment of the invention includes a method of simulating a control-dataflow graph that includes building an internal representation of the control-dataflow graph that includes one or more dataflow code blocks, and simulating the control-dataflow graph as a sequence of code block dataflow executions, where control is passed from one code block to another code block based on the output value of the code block until EXIT is reached.
摘要翻译：本发明的实施例包括一种模拟混合指令处理器和可重构处理器实现的算法的方法，该算法利用模拟可重构处理器及其资源的运行时可选仿真库，以及模拟该算法的可重构逻辑的控制数据流仿真器。本发明的另一实施例包括一种模拟控制数据流图的方法，该方法包括构建包括一个或多个数据流代码块的控制数据流图的内部表示，以及将该控制数据流图模拟为代码块数据流序列执行，其中基于代码块的输出值，直到达到EXIT，控制从一个代码块传递到另一代码块。

7. 发明授权

US07124211B2 System and method for explicit communication of messages between processes running on different nodes in a clustered multiprocessor system 有权
标题翻译：用于在群集多处理器系统中运行在不同节点上的进程之间显式通信消息的系统和方法
公开(公告)号：US07124211B2
公开(公告)日：2006-10-17
申请号：US10278345
申请日：2002-10-23
申请人： Christopher Dickson , David Caliga , James O'Connor , Daniel Poznanovic
发明人： Christopher Dickson , David Caliga , James O'Connor , Daniel Poznanovic
IPC分类号： G06F13/28
CPC分类号： G06F9/544 , G06F13/1663 , G06F13/28
摘要： Embodiments of the invention include a mechanism for explicit communication in a clustered multiprocessor system that supports low-latency, protected, user-mode, communication across the machine boundaries of a clustered multiprocessor. Data transport may be accomplished over persistent, unidirectional, point-to point connections, each of which may be embodied in a small amount of state at each end, along with a statically allocated per-connection memory buffer, which may be directly accessible to the transport mechanism at both ends of each notional link. System Memory protection may be afforded by operating system (“OS”) facilitated allocation of both restricted control of the network interface, and responsibility for data transport, to an application thread that may execute in the context of the processor-managed virtual address space. Connection buffer protection may be afforded by restricting access to connection state to those entries associated with the currently controlling thread.
摘要翻译：本发明的实施例包括用于在集群多处理器的机器边界上支持低延迟，受保护的用户模式通信的集群多处理器系统中的显式通信的机制。数据传输可以通过持久的，单向的点到点连接来实现，每个连接可以以每一端的少量状态来实现，以及静态分配的每连接存储器缓冲器，其可以直接访问每个名义链接两端的运输机制。系统可以通过操作系统（“OS”）提供对网络接口的受限控制和数据传输责任的分配给可在处理器管理的虚拟地址空间的上下文中执行的应用程序线程的内存保护。可以通过限制对与当前控制线程相关联的那些条目的连接状态的访问来提供连接缓冲器保护。

8. 发明授权

US07167976B2 Interface for integrating reconfigurable processors into a general purpose computing system 有权
标题翻译：用于将可重构处理器集成到通用计算系统中的接口
公开(公告)号：US07167976B2
公开(公告)日：2007-01-23
申请号：US11140718
申请日：2005-05-31
申请人： Daniel Poznanovic
发明人： Daniel Poznanovic
IPC分类号： G06F13/14
CPC分类号： G06F15/7867 , G06F1/24 , G06F9/3879 , G06F9/3897
摘要： The present invention describes a method and system for an interface for integrating reconfigurable processors into a general purpose computing system. In particular, the system resides in a computer system containing standard instruction processors, as well as reconfigurable processors. The interface includes a command processor, a command list memory, various registers, a direct memory access engine, a translation look-aside buffer, a dedicated section of common memory, and a dedicated memory. The interface is controlled via commands from a command list that is created during compilation of a user application, or various direct commands.
摘要翻译：本发明描述了一种用于将可重构处理器集成到通用计算系统中的接口的方法和系统。特别地，该系统驻留在包含标准指令处理器的计算机系统以及可重新配置的处理器中。接口包括命令处理器，命令列表存储器，各种寄存器，直接存储器访问引擎，翻译后备缓冲器，公共存储器的专用部分和专用存储器。该接口通过来自用户应用程序编译期间创建的命令列表的命令或各种直接命令进行控制。

9. 发明授权

US07155602B2 Interface for integrating reconfigurable processors into a general purpose computing system 有权
公开(公告)号：US07155602B2
公开(公告)日：2006-12-26
申请号：US10011835
申请日：2001-12-05
申请人： Daniel Poznanovic
发明人： Daniel Poznanovic
IPC分类号： G06F9/45
CPC分类号： G06F15/7867 , G06F1/24 , G06F9/3879 , G06F9/3897
摘要： The present invention describes a method and system for an interface for integrating reconfigurable processors into a general purpose computing system. In particular, the system resides in a computer system containing standard instruction processors, as well as reconfigurable processors. The interface includes a command processor, a command list memory, various registers, a direct memory access engine, a translation look-aside buffer, a dedicated section of common memory, and a dedicated memory. The interface is controlled via commands from a command list that is created during compilation of a user application, or various direct commands.

10. 发明申请

US20050223213A1 Interface for integrating reconfigurable processors into a general purpose computing system 有权
标题翻译：用于将可重构处理器集成到通用计算系统中的接口
公开(公告)号：US20050223213A1
公开(公告)日：2005-10-06
申请号：US11140718
申请日：2005-05-31
申请人： Daniel Poznanovic
发明人： Daniel Poznanovic
IPC分类号： G06F1/24 , G06F9/38 , G06F15/78
CPC分类号： G06F15/7867 , G06F1/24 , G06F9/3879 , G06F9/3897
摘要： The present invention describes a method and system for an interface for integrating reconfigurable processors into a general purpose computing system. In particular, the system resides in a computer system containing standard instruction processors, as well as reconfigurable processors. The interface includes a command processor, a command list memory, various registers, a direct memory access engine, a translation look-aside buffer, a dedicated section of common memory, and a dedicated memory. The interface is controlled via commands from a command list that is created during compilation of a user application, or various direct commands.
摘要翻译：本发明描述了一种用于将可重构处理器集成到通用计算系统中的接口的方法和系统。特别地，该系统驻留在包含标准指令处理器的计算机系统以及可重新配置的处理器中。接口包括命令处理器，命令列表存储器，各种寄存器，直接存储器访问引擎，翻译后备缓冲器，公共存储器的专用部分和专用存储器。该接口通过来自用户应用程序编译期间创建的命令列表的命令或各种直接命令进行控制。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式