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1. 发明申请

US20050167838A1 DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于减少半导体器件中有效介电常数的器件和方法
公开(公告)号：US20050167838A1
公开(公告)日：2005-08-04
申请号：US10707996
申请日：2004-01-30
申请人： Daniel Edelstein , Matthew Colburn , Edward Cooney , Timothy Dalton , John Fitzsimmons , Jeffrey Gambino , Elbert Huang , Michael Lane , Vincent McGahay , Lee Nicholson , Satyanarayana Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas Shaw , Andrew Simon , Anthony Stamper
发明人： Daniel Edelstein , Matthew Colburn , Edward Cooney , Timothy Dalton , John Fitzsimmons , Jeffrey Gambino , Elbert Huang , Michael Lane , Vincent McGahay , Lee Nicholson , Satyanarayana Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas Shaw , Andrew Simon , Anthony Stamper
IPC分类号： H01L21/033 , H01L21/302 , H01L21/311 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/522 , H01L23/532 , H01L29/40
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lanes and vias
摘要翻译：一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。还可以使用超光刻阻挡掩模。另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。可能禁止在划线车道和通道上或附近形成间隙

2. 发明申请

US20050127514A1 Line level air gaps 失效
标题翻译：线路气隙
公开(公告)号：US20050127514A1
公开(公告)日：2005-06-16
申请号：US10731377
申请日：2003-12-08
申请人： Shyng-Tsong Chen , Stefanie Chiras , Matthew Colburn , Timothy Dalton , Jeffrey Hedrick , Elbert Huang , Kaushik Kumar , Michael Lane , Kelly Malone , Chandrasekhar Narayan , Satyanarayana Nitta , Sampath Purushothaman , Robert Rosenberg , Christy Tyberg , Roy Yu
发明人： Shyng-Tsong Chen , Stefanie Chiras , Matthew Colburn , Timothy Dalton , Jeffrey Hedrick , Elbert Huang , Kaushik Kumar , Michael Lane , Kelly Malone , Chandrasekhar Narayan , Satyanarayana Nitta , Sampath Purushothaman , Robert Rosenberg , Christy Tyberg , Roy Yu
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L29/40
CPC分类号： H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.
摘要翻译：在多电平微电子集成电路中，空气包括永久线路电介质，超低K材料通过电介质。在通过清洁热分解除去牺牲材料并通过IC结构中的孔隙率辅助副产物扩散后，将空气供应到线路电平。任选地，空气也包括在通孔级电介质中的孔隙中。通过将空气结合到本发明产生的程度，使层内和层间介电值最小化。

3. 发明申请

US20060258147A1 Method of forming closed air gap interconnects and structures formed thereby 有权
公开(公告)号：US20060258147A1
公开(公告)日：2006-11-16
申请号：US11405287
申请日：2006-04-17
申请人： Matthew Colburn , Timothy Dalton , Elbert Huang , Simon Karecki , Anna Karecki , Satya Nitta , Sampath Purushothaman , Katherine Saenger , Maheswaran Surendra
发明人： Matthew Colburn , Timothy Dalton , Elbert Huang , Simon Karecki , Anna Karecki , Satya Nitta , Sampath Purushothaman , Katherine Saenger , Maheswaran Surendra
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/76807 , H01L21/7682 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.

4. 发明申请

US20050062165A1 Method of forming closed air gap interconnects and structures formed thereby 有权
标题翻译：形成闭合气隙互连件和由此形成的结构的方法
公开(公告)号：US20050062165A1
公开(公告)日：2005-03-24
申请号：US10666564
申请日：2003-09-19
申请人： Katherine Saenger , Maheswaran Surendra , Simon Karecki , Satya Nitta , Sampath Purushothaman , Matthew Colburn , Timothy Dalton , Elbert Huang
发明人： Katherine Saenger , Maheswaran Surendra , Simon Karecki , Satya Nitta , Sampath Purushothaman , Matthew Colburn , Timothy Dalton , Elbert Huang
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L21/4763
CPC分类号： H01L21/76807 , H01L21/7682 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.
摘要翻译：描述了形成闭合气隙互连结构的方法。与存在于所述互连结构的其余部分的一个或多个牺牲介电质制成的互连线下永久支撑电介质的区域和周围的互连通孔的起始结构，覆盖有其使用模版具有规则穿孔的电介质阻挡孔阵列然后通过电介质阻挡层中的孔提取牺牲电介质，使得互连线基本上被除了线下方的支撑电介质的区域之外的空气包围。通过沉积第二阻挡电介质来封闭盖层中的孔，从而形成封闭的气隙。描述该方法的几个实施例和所得到的结构。

5. 发明申请

US20060267208A1 Method of forming closed air gap interconnects and structures formed thereby 失效
标题翻译：形成闭合气隙互连件和由此形成的结构的方法
公开(公告)号：US20060267208A1
公开(公告)日：2006-11-30
申请号：US11405283
申请日：2006-04-17
申请人： Matthew Colburn , Timothy Dalton , Elbert Huang , Simon Karecki , Satya Nitta , Sampath Purushothaman , Katherine Saenger , Maheswaran Surendra
发明人： Matthew Colburn , Timothy Dalton , Elbert Huang , Simon Karecki , Satya Nitta , Sampath Purushothaman , Katherine Saenger , Maheswaran Surendra
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76807 , H01L21/7682 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.
摘要翻译：描述了形成闭合气隙互连结构的方法。在互连线下方由永久支撑电介质的区域构成的起始结构和在互连结构的其余部分中存在的具有一个或多个牺牲电介质的周围的互连通孔被封装有电介质阻挡层，其使用具有规则的模板孔阵列然后通过电介质阻挡层中的孔提取牺牲电介质，使得互连线基本上被除了线下方的支撑电介质的区域之外的空气包围。通过沉积第二阻挡电介质来封闭盖层中的孔，从而形成封闭的气隙。描述该方法的几个实施例和所得到的结构。

6. 发明申请

US20070181974A1 PLANAR VERTICAL RESISTOR AND BOND PAD RESISTOR AND RELATED METHOD 有权
标题翻译：平面垂直电阻和焊盘电阻及相关方法
公开(公告)号：US20070181974A1
公开(公告)日：2007-08-09
申请号：US11307404
申请日：2006-02-06
申请人： Douglas Coolbaugh , Timothy Dalton , Daniel Edelstein , Ebenezer Eshun , Jeffrey Gambino , Kevin Petrarca , Anthony Stamper , Richard Volant
发明人： Douglas Coolbaugh , Timothy Dalton , Daniel Edelstein , Ebenezer Eshun , Jeffrey Gambino , Kevin Petrarca , Anthony Stamper , Richard Volant
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L28/20 , H01L23/5228 , H01L23/53238 , H01L23/53295 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.
摘要翻译：公开了避免半导体器件小型化的问题的电阻器及相关方法。在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。这两个实施方案可以单独使用或一起使用。还公开了用于产生电阻器的相关方法。

7. 发明申请

US20080054393A1 METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE 有权
标题翻译：无平面化和相关半导体器件制造被动元件的方法
公开(公告)号：US20080054393A1
公开(公告)日：2008-03-06
申请号：US11928798
申请日：2007-10-30
申请人： Anil Chinthakindi , Timothy Dalton , Ebenezer Eshun , Jeffrey Gambino , Anthony Stamper , Kunal Vaed
发明人： Anil Chinthakindi , Timothy Dalton , Ebenezer Eshun , Jeffrey Gambino , Anthony Stamper , Kunal Vaed
IPC分类号： H01L29/00 , H01L21/02
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在所述电介质层中形成通过所述介电层与所述无源元件的互连以及与所述虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

8. 发明申请

US20070241424A1 VERTICAL PARALLEL PLATE CAPACITOR USING SPACER SHAPED ELECTRODES AND METHOD FOR FABRICATION THEREOF 有权
标题翻译：使用间隔型电极的垂直平行平板电容器及其制造方法
公开(公告)号：US20070241424A1
公开(公告)日：2007-10-18
申请号：US11279434
申请日：2006-04-12
申请人： Timothy Dalton , Jeffrey Gambino , Anthony Stamper
发明人： Timothy Dalton , Jeffrey Gambino , Anthony Stamper
IPC分类号： H01L29/00
CPC分类号： H01G4/33 , H01G4/236 , H01L28/91 , Y10T29/435
摘要： A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalks of the aperture. A pair of capacitor plates is located upon the pair of opposite sidewalks of the aperture and contacting the pair of conductor interconnection layers, but not filling the aperture. A capacitor dielectric layer is located interposed between the pair of capacitor plates and filling the aperture. The pair of capacitor plates may be formed using an anisotropic unmasked etch followed by a masked trim etch. Alternatively, the pair of capacitor plates may be formed using an unmasked anisotropic etch only, when the pair of opposite sidewalks of the aperture is vertical and separated by a second pair of opposite sidewalks that is outward sloped.
摘要翻译：电容器结构使用位于电介质层内的开口依次位于衬底上。嵌入电介质层内的一对导体互连层终止于孔的一对相对的人行道。一对电容器板位于孔的一对相对的人行道上，并接触一对导体互连层，但不填充孔。电容器介质层位于一对电容器板之间并填充孔。可以使用各向异性无掩模蚀刻，然后进行掩模修整蚀刻来形成该对电容器板。或者，一对电容器板可以仅使用未屏蔽的各向异性蚀刻形成，当孔的一对相对的人行道是垂直的并且被向外倾斜的第二对相对的人行道分隔开时。

9. 发明申请

US20080047118A1 VERTICAL PARALLEL PLATE CAPACITOR USING SPACER SHAPED ELECTRODES AND METHOD FOR FABRICATION THEREOF 审中-公开
标题翻译：使用间隔型电极的垂直平行平板电容器及其制造方法
公开(公告)号：US20080047118A1
公开(公告)日：2008-02-28
申请号：US11924807
申请日：2007-10-26
申请人： Timothy Dalton , Jeffrey Gambino , Anthony Stamper
发明人： Timothy Dalton , Jeffrey Gambino , Anthony Stamper
IPC分类号： H01G7/00
CPC分类号： H01G4/33 , H01G4/236 , H01L28/91 , Y10T29/435
摘要： A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalls of the aperture. A pair of capacitor plates is located upon the pair of opposite sidewalls of the aperture and contacting the pair of conductor interconnection layers, but not filling the aperture. A capacitor dielectric layer is located interposed between the pair of capacitor plates and filling the aperture. The pair of capacitor plates may be formed using an anisotropic unmasked etch followed by a masked trim etch. Alternatively, the pair of capacitor plates may be formed using an unmasked anisotropic etch only, when the pair of opposite sidewalls of the aperture is vertical and separated by a second pair of opposite sidewalls that is outward sloped.
摘要翻译：电容器结构使用位于电介质层内的开口依次位于衬底上。嵌入电介质层内的一对导体互连层终止于孔的一对相对的侧壁。一对电容器板位于孔的一对相对的侧壁上，并接触一对导体互连层，但不填充孔。电容器介质层位于一对电容器板之间并填充孔。可以使用各向异性无掩模蚀刻，然后进行掩模修整蚀刻来形成该对电容器板。或者，一对电容器板可以仅使用未屏蔽的各向异性蚀刻形成，当孔的一对相对的侧壁是垂直的并且被向外倾斜的第二对相对的侧壁隔开时。

10. 发明申请

US20070267698A1 DUAL WIRED INTEGRATED CIRCUIT CHIPS 有权
标题翻译：双线集成电路板
公开(公告)号：US20070267698A1
公开(公告)日：2007-11-22
申请号：US11774853
申请日：2007-07-09
申请人： Kerry Bernstein , Timothy Dalton , Jeffrey Gambino , Mark Jaffe , Paul Kartschoke , Anthony Stamper
发明人： Kerry Bernstein , Timothy Dalton , Jeffrey Gambino , Mark Jaffe , Paul Kartschoke , Anthony Stamper
IPC分类号： H01L27/088 , H01L21/84
CPC分类号： H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/522 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.
摘要翻译：具有相对侧的布线电平的半导体器件以及制造与相对侧的器件和布线电平接触的半导体结构的方法。该方法包括在绝缘体上硅衬底上制造器件，其中器件的第一接触和第一侧的第一接触处的布线电平，去除下硅层以暴露所述掩埋氧化物层，形成第二接触器件通过掩埋氧化物层形成掩埋氧化物层上方的布线电平到第二触点。

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