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    • 2. 发明授权
    • Multiple frequency phase-locked loop clock generator with stable
transitions between frequencies
    • 频率间稳定转换的多频锁相环时钟发生器
    • US5142247A
    • 1992-08-25
    • US741083
    • 1991-08-06
    • Henry F. Lada, Jr.Hung Q. LeJames H. GarrettJohn M. Gromala
    • Henry F. Lada, Jr.Hung Q. LeJames H. GarrettJohn M. Gromala
    • H03L7/18
    • H03L7/18
    • A phase-locked loop (PLL) clock generator circuit which is capable of changing the frequency of its outpt clock signal in a stable fashion. Selection of the frequency of the output clock signal is made by way of a selectable frequency divider coupled between the reference clock signal and an input of the PLL, with another frequency divider in the feedback loop of the PLL; each of these frequency dividers are selectable according to a signal on a select bus, translated by way of a ROM look-up table. The circuit also includes a multiplexer having a first input coupled to the PLL output, and a second input coupled to a stable clock signal, for example to the referenc clock signal or to the output of a fixed frequency PLL. The conrol input of the multiplexer is controlled by a state machine which monitors the select bus. Responsive to detection of a transition of the select bus, indicating a new frequency, the state machine issues a pulse to the control input of the multiplexer to cause it to select the stable clock signal for sufficient time to allow the PLL to acquire and lock onto the new frequency, after which the multiplexer again selects the PLL output as the output clock signal. As a result, the unstable and non-linear behavior at the PLL output does not appear at the output of the circuit, with a stable clock signal at a safe frequency appearing thereat during the PLL transitional cycles.
    • 锁相环(PLL)时钟发生器电路,其能够以稳定的方式改变其外部时钟信号的频率。 输出时钟信号的频率选择通过耦合在参考时钟信号和PLL的输入端之间的可选择的分压器与PLL的反馈环路中的另一个分频器进行; 这些分频器中的每一个可以根据选择总线上的信号进行选择,通过ROM查找表进行转换。 电路还包括具有耦合到PLL输出的第一输入和耦合到稳定时钟信号的第二输入的多路复用器,例如耦合到参考时钟信号或固定频率PLL的输出。 多路复用器的控制输入由监视选择总线的状态机控制。 响应于检测选择总线的转换,指示新的频率,状态机向多路复用器的控制输入端发出脉冲,使其选择稳定的时钟信号足够的时间以允许PLL获取并锁定到 新的频率,之后复用器再次选择PLL输出作为输出时钟信号。 因此,PLL输出端的不稳定和非线性特性不会出现在电路的输出端,稳定的时钟信号出现在PLL过渡周期内的安全频率。
    • 3. 发明授权
    • Method and apparatus for displaying different shades of gray on a liquid
crystal display
    • 用于在液晶显示器上显示不同灰度的方法和装置
    • US5245328A
    • 1993-09-14
    • US597814
    • 1990-10-15
    • James H. Garrett
    • James H. Garrett
    • G09G3/20G09G3/36H04N3/12
    • G09G3/3611H04N3/127G09G2320/0247G09G3/2025G09G3/2051
    • A method and apparatus are disclosed which provide a means for both spatially and temporarily resolving the on/off states of a two-state display device such as a liquid crystal display to provide apparent shades of gray. A particular feature of this method is that the cycling between on and off states is not performed in a single, repetitive pattern. Rather, a pattern is utilized which repeats only after many cycles. Additionally, when the 10 method disclosed herein is utilized, adjacent pixels, when selected to display the same shade of gray, do not cycle on and off in synchronization, but rather utilize out-of-phase cycling patterns. This spatial resolution reduces perceived flicker in the display and provides a more stable image. In one embodiment, sixteen shades of gray are provided. The shades are generated by cycling individual pixels such that when averaged over time, the duty cycles of such cycling are 0, 1/9, 1/7, 1/5, 2/7, 1/3, 2/5, 7/15, 8/15, 3/5, 2/3, 5/7, 4/5, 6/7, 8/9 and 1.
    • 公开了一种方法和装置,其提供用于空间和临时分辨诸如液晶显示器的两状态显示装置的开/关状态的装置,以提供明显的灰度。 该方法的一个特点是,在单独的重复模式中不执行打开和关闭状态之间的循环。 相反,使用仅在许多周期后重复的模式。 此外,当使用本文公开的10种方法时,相邻像素当被选择以显示相同的灰色阴影时,不会同步地进行循环,而是利用异相循环模式。 该空间分辨率降低了显示屏中的感知闪烁,并提供了更稳定的图像。 在一个实施例中,提供了十六个灰色阴影。 通过循环单个像素来生成阴影,使得当随时间平均时,这种循环的占空比为0,1/9,1/7,1/5,2/7,1/3,2 / 5,7 / 15,8/15,3/5,2/3,5/7,4/5,6/7,8/9和1。