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1. 发明授权

US5898232A Input/output section of an integrated circuit having separate power down capability 失效
标题翻译：具有独立断电功能的集成电路的输入/输出部分
公开(公告)号：US5898232A
公开(公告)日：1999-04-27
申请号：US555263
申请日：1995-11-08
申请人： Daniel B. Reents , Mark T. Ellis
发明人： Daniel B. Reents , Mark T. Ellis
IPC分类号： G06F1/24 , G06F1/32 , H02J1/10 , G06F1/00
CPC分类号： G06F1/325 , G06F1/3203 , Y02B60/32 , Y10T307/305 , Y10T307/615
摘要： A personal information device is provided, which includes an integrated circuit coupled to a variety of peripheral devices. The integrated circuit is configured with a core section and one or more input/output sections. The core section is powered independently of the input/output sections, allowing selective power down of peripheral components coupled to the integrated circuit without the use of external buffers. The input/output sections are configured with unique input/output circuits which perform the buffering task. The integrated circuit is further configured with a partial reset. The partial reset selectively forces portions of the integrated circuit to an initial state while other portions continue to operate. One particular embodiment of the integrated circuit is configured with a CPU and an RTC unit which comprises configuration RAM and a real time clock facility. When the partial reset is activated, the RTC unit is not reset but the CPU is reset. When the personal information device detects the need to conserve power, the power supply or a reset unit asserts the partial reset. Additionally, the power supply powers down selected peripheral components and the associated input/output driver sections while retaining power to the core section. Time/date and configuration information is therefore retained and power consumption is reduced.
摘要翻译：提供个人信息设备，其包括耦合到各种外围设备的集成电路。集成电路配置有核心部分和一个或多个输入/输出部分。核心部分独立于输入/输出部分供电，允许在不使用外部缓冲器的情况下连接到集成电路的外设组件选择性关断电源。输入/输出部分配置有执行缓冲任务的唯一输入/输出电路。集成电路进一步配置有部分复位。部分复位选择性地将集成电路的部分强制为初始状态，而其他部分继续操作。集成电路的一个具体实施例配置有CPU和RTC单元，其包括配置RAM和实时时钟设施。当部分复位被激活时，RTC单元不复位，但CPU被复位。当个人信息设备检测到需要节省电力时，电源或复位单元断言部分重置。此外，电源在保持对核心部分的电源的同时降低所选择的外围组件和相关的输入/输出驱动器部分。因此，保留时间/日期和配置信息并降低功耗。

2. 发明授权

US5860125A Integrated circuit including a real time clock, configuration RAM, and memory controller in a core section which receives an asynchronous partial reset and an asynchronous master reset 失效
标题翻译：集成电路包括接收异步部分复位和异步主复位的核心部分中的实时时钟，配置RAM和存储器控制器
公开(公告)号：US5860125A
公开(公告)日：1999-01-12
申请号：US555264
申请日：1995-11-08
申请人： Daniel B. Reents
发明人： Daniel B. Reents
IPC分类号： G06F1/24 , G06F1/32 , G06F12/00
CPC分类号： G06F1/24
摘要： An integrated circuit is provided which comprises a core section, a plurality of input/output sections, and a pair of reset inputs. The first reset input is a master reset which initializes the entire integrated circuit. The second reset input is a partial reset. The partial reset initializes a portion of the integrated circuit while other portions remain in operation. The core section can include a plurality of subsystems such as a real time clock facility, a configuration RAM, and a DRAM memory controller. The real time clock facility and configuration RAM are not affected by the partial reset. Accordingly, the real time clock is maintained during partial reset, thereby maintaining accurate time/date and configuration data during partial reset. The DRAM controller is optionally reset based on a configuration bit stored in a configuration register in one of the plurality of subsystems. When not reset, the DRAM controller provides refresh to an array of DRAM memory cells, thereby maintaining the data stored within the DRAM memory cells. The integrated circuit can be configured into a personal information device, wherein a power conservation method can then be applied by resetting portions of the integrated circuit and powering down peripheral components and input/output driver sections associated with the reset portions. Additionally, discrete buffer devices are no longer required between the integrated circuit and the peripheral component.
摘要翻译：提供一种集成电路，其包括核心部分，多个输入/输出部分和一对复位输入。第一个复位输入是初始化整个集成电路的主复位。第二个复位输入是部分复位。部分复位初始化集成电路的一部分，而其他部分保持运行。核心部分可以包括多个子系统，例如实时时钟设施，配置RAM和DRAM存储器控制器。实时时钟设备和配置RAM不受部分重置的影响。因此，在部分复位期间保持实时时钟，从而在部分复位期间保持精确的时间/日期和配置数据。可选地，DRAM控制器基于存储在多个子系统之一中的配置寄存器中的配置位来重置。当不再复位时，DRAM控制器向DRAM存储器单元阵列提供刷新，从而保持存储在DRAM存储单元内的数据。集成电路可以被配置为个人信息设备，其中然后可以通过重置集成电路的部分并对与复位部分相关联的外围组件和输入/输出驱动器部分供电来施加功率节省方法。此外，集成电路和外围组件之间不再需要离散缓冲器件。

3. 发明授权

US07328270B1 Communication protocol processor having multiple microprocessor cores connected in series and dynamically reprogrammed during operation via instructions transmitted along the same data paths used to convey communication data 有权
标题翻译：通信协议处理器具有串联连接的多个微处理器核心并且在操作期间通过沿着用于传送通信数据的相同数据路径发送的指令而动态重新编程
公开(公告)号：US07328270B1
公开(公告)日：2008-02-05
申请号：US09257521
申请日：1999-02-25
申请人： Daniel B. Reents , Donald G. Craycraft , Carl K. Wakeland
发明人： Daniel B. Reents , Donald G. Craycraft , Carl K. Wakeland
IPC分类号： G06F15/177 , G06F15/16
CPC分类号： G06F15/16
摘要： A communication protocol processor is presented including a transmit unit and a receive unit, each having multiple microprocessor cores connected in series. Each microprocessor core performs an operation upon a stream of communication data, conducted along a data path, according to instructions and associated data stored within a code memory unit. A change in the operation performed by a given microprocessor core is effectuated during communication protocol processor operation by transmitting new instructions and associated data to the microprocessor core along the data path. The new instructions and data modify the existing instructions and associated data stored within the code memory unit. The transmit unit of the communication protocol processor receives packet (i.e., transmit) data in parallel units and produces a framed serial transmit data stream. Each microprocessor core of the transmit unit is assigned one or more tasks which must be accomplished in sequence in order to encapsulate the transmit data stream into frames in accordance with a selected communication protocol. The receive unit receives a framed serial receive data stream and produces packet (i.e., receive) data in parallel units. Each microprocessor core of the receive unit is assigned one or more tasks which must be accomplished in sequence in order to extract receive data from the framed serial receive data stream in accordance with the selected communication protocol. The communication protocol processor may be included within a microcontroller, and the microcontroller employed within a network interface unit (NIU).
摘要翻译：提出了一种通信协议处理器，其包括发送单元和接收单元，每个发送单元和接收单元具有串联连接的多个微处理器核心。每个微处理器核心根据存储在代码存储器单元内的指令和关联数据沿着数据路径进行通信数据流的操作。通过在通信协议处理器操作期间通过沿着数据路径向微处理器核发送新的指令和相关联的数据来实现由给定微处理器核心执行的操作的改变。新的指令和数据修改存储在代码存储单元内的现有指令和相关数据。通信协议处理器的发送单元以并行单位接收分组（即发送）数据，并产生成帧的串行发送数据流。发送单元的每个微处理器核被分配一个或多个必须按顺序完成的任务，以便根据所选择的通信协议将发送数据流封装成帧。接收单元接收成帧串行接收数据流并以并行单位产生分组（即，接收）数据。接收单元的每个微处理器核心被分配一个或多个必须按顺序完成的任务，以便根据所选择的通信协议从成帧的串行接收数据流中提取接收数据。通信协议处理器可以包括在微控制器内，并且微控制器在网络接口单元（NIU）内使用。

4. 发明授权

US06978412B1 Method and apparatus for adaptive frame tracking 有权
标题翻译：自适应帧跟踪的方法和装置
公开(公告)号：US06978412B1
公开(公告)日：2005-12-20
申请号：US09375120
申请日：1999-08-16
申请人： Daniel B. Reents , Patrick Maupin
发明人： Daniel B. Reents , Patrick Maupin
IPC分类号： H04L1/00 , G08C25/00 , H03M13/00
CPC分类号： H04L1/0002
摘要： The present invention provides for an apparatus and a method for performing adaptive frame tracking. The present invention comprises an adaptive frame tracking unit capable of receiving and sending at least one data packet and automatically adjusting a data rate of the data packet by determining if there exists at least one data frame error and correcting for the data frame error in response to a determination that there exists at least one the data frame error.
摘要翻译：本发明提供一种用于执行自适应帧跟踪的装置和方法。本发明包括一种自适应帧跟踪单元，其能够接收和发送至少一个数据分组，并且通过确定是否存在至少一个数据帧错误并且响应于所述数据帧错误来校正数据帧错误来自动调整数据分组的数据速率确定存在至少一个数据帧错误。

5. 发明授权

US5561384A Input/output driver circuit for isolating with minimal power consumption a peripheral component from a core section 失效
标题翻译：输入/输出驱动器电路，用于从芯部隔离最小功耗的外围元件
公开(公告)号：US5561384A
公开(公告)日：1996-10-01
申请号：US555217
申请日：1995-11-08
申请人： Daniel B. Reents , Michael S. Quimby , Carl K. Wakeland
发明人： Daniel B. Reents , Michael S. Quimby , Carl K. Wakeland
IPC分类号： H03K19/00 , H03K3/00
CPC分类号： H03K19/0016
摘要： Within an integrated circuit, an input/output driver circuit is provided. The input/output driver circuit is configured to provide electrical isolation and power savings when the integrated circuit is configured into a computer system such as a personal information device. By providing a mechanism permitting removal of power from the driver circuit, the integrated circuit inhibits current flow from the integrated circuit into a powered-down peripheral device. A force term is activated, when electrical isolation is desired, to inhibit current flow into or from the integrated circuit via an input/output pad voltage level. A power savings is enabled by allowing the power down of peripheral devices coupled to the integrated circuit without the need for external buffer circuits.
摘要翻译：在集成电路中，提供输入/输出驱动器电路。输入/输出驱动器电路被配置为当集成电路被配置到诸如个人信息设备的计算机系统中时提供电隔离和功率节省。通过提供允许从驱动器电路移除电力的机构，集成电路抑制从集成电路到掉电的外围设备的电流流动。当需要进行电气隔离时，强制项被激活，以阻止通过输入/输出焊盘电压电平流入或流出集成电路的电流。通过允许连接到集成电路的外围设备断电而不需要外部缓冲电路，可实现省电。

6. 发明授权

US5534889A Circuit for controlling bias voltage used to regulate contrast in a display panel 失效
标题翻译：用于控制用于调节显示面板对比度的偏置电压的电路
公开(公告)号：US5534889A
公开(公告)日：1996-07-09
申请号：US119422
申请日：1993-09-10
申请人： Daniel B. Reents , Patrick R. Cooper , James H. Garrett , Philip J. McKenzie
发明人： Daniel B. Reents , Patrick R. Cooper , James H. Garrett , Philip J. McKenzie
IPC分类号： G09G3/36 , G09G5/00
CPC分类号： G09G3/36
摘要： A liquid crystal display (LCD) panel which has its contrast controlled through the use of a pulse width modulation (PWM) circuit contained in the video controller and a contrast control circuit. In response to a particular video refresh mode, the PWM circuit modulates the pulse width of a signal that is an input to the contrast control circuit. The pulse width is changed by the use of a base contrast register and two offset registers. Depending on the video mode, the base register is used alone or is combined with one of the offset registers to provide a signal to indicate the duty cycle of the signal. The pulse width modulated signal is converted to a DC bias contrast voltage which is provided to the LCD panel.
摘要翻译：通过使用包含在视频控制器中的脉冲宽度调制（PWM）电路和对比度控制电路来控制其对比度的液晶显示器（LCD）面板。响应于特定的视频刷新模式，PWM电路调制作为对比度控制电路的输入的信号的脉冲宽度。通过使用基本对比度寄存器和两个偏移寄存器来改变脉冲宽度。根据视频模式，基本寄存器单独使用或与其中一个偏移寄存器组合，以提供信号以指示信号的占空比。脉冲宽度调制信号被转换为提供给LCD面板的DC偏压对比度电压。

7. 发明授权

US5455907A Buffering digitizer data in a first-in first-out memory 失效
标题翻译：以先进先出的存储器缓冲数字化仪数据
公开(公告)号：US5455907A
公开(公告)日：1995-10-03
申请号：US119718
申请日：1993-09-10
申请人： Randall L. Hess , Gaines C. Teague , Patrick R. Cooper , Daniel B. Reents , Hung Q. Le
发明人： Randall L. Hess , Gaines C. Teague , Patrick R. Cooper , Daniel B. Reents , Hung Q. Le
IPC分类号： G06F3/033 , G06F3/048 , G06F15/00
CPC分类号： G06F3/04883
摘要： A computer system with a digitizer based screen display in which the digitizer data is buffered through a first-in first-out memory (FIFO). The processor is only interrupted when a full digitizer data packet is available in the FIFO, rather than being interrupted on each data byte available in the FIFO. The FIFO can hold multiple digitizer data packets, so that data is not lost should the processor in the computer system be unable to immediately handle these digitizer data packets. The system also provides a filter in a separate controller that examines each digitizer data packet to determine if the pen is in a predefined screen location that performs a prespecified function. If so, rather than pass the digitizer data packet to the system processor through the FIFO, the command is passed through a separate register to the processor based on the "hotspot" touched on the screen.
摘要翻译：一种具有基于数字化仪的屏幕显示的计算机系统，其中数字转换器数据通过先进先出存储器（FIFO）进行缓冲。只有当FIFO中有一个完整的数字转换器数据包可用时，才会中断处理器，而不是在FIFO中可用的每个数据字节中断处理器。 FIFO可以容纳多个数字转换器数据包，以便计算机系统中的处理器无法立即处理这些数字化数据包时数据不会丢失。该系统还在单独的控制器中提供一个过滤器，该过滤器检查每个数字化仪数据包，以确定笔是否在执行预定功能的预定屏幕位置。如果是，则不是通过FIFO将数字转换器数据包传递给系统处理器，而是根据触摸屏幕上的“热点”将命令传递给处理器。

8. 发明授权

US07088680B1 System and method for digital communication via a time division multiplexed serial data stream 有权
标题翻译：通过时分复用串行数据流进行数字通信的系统和方法
公开(公告)号：US07088680B1
公开(公告)日：2006-08-08
申请号：US09228445
申请日：1999-01-11
申请人： William W. Freitag, Jr. , Daniel B. Reents
发明人： William W. Freitag, Jr. , Daniel B. Reents
IPC分类号： H04J3/14
CPC分类号： H04J3/04 , H04J3/0685 , H04J3/1623 , H04J3/247 , H04L7/0008
摘要： A system and method are presented for digital communication via a time division multiplexed serial data stream. A serial communication system according to the present invention includes a serial communication controller having a set of functional units each configured to perform a specific function of a serial communication protocol. The functional units are operably coupled in series in order to produce digital data according to the serial communication protocol. The set of functional units operates alternately upon an active one of the multiple serial data channels within the time division multiplexed serial data stream. Each functional unit may be a state machine including one or more programmable registers for storing state information which determines the operating state of the functional unit. An active channel transition from a first data channel to a second data channel may be accomplished by saving state information associated with the first data channel and “restoring” saved state information associated with the second data channel. A memory unit coupled to each functional unit may include a separate portion allocated to each of the multiple serial data channels. State information may be retrieved from the functional units and stored in the portion of the memory unit allocated to the first data channel. State information may then be retrieved from the portion of the memory unit allocated to the second data channel and stored within the memory elements of the functional units, thus accomplishing the state “restoring” activity.
摘要翻译：提出了一种通过时分复用串行数据流进行数字通信的系统和方法。根据本发明的串行通信系统包括具有一组功能单元的串行通信控制器，每个功能单元被配置为执行串行通信协议的特定功能。功能单元可操作地串联耦合，以便根据串行通信协议产生数字数据。所述功能单元组在时分多路复用串行数据流内的多个串行数据信道中的有效一个上交替工作。每个功能单元可以是包括用于存储确定功能单元的操作状态的状态信息的一个或多个可编程寄存器的状态机。可以通过保存与第一数据信道相关联的状态信息和“恢复”与第二数据信道相关联的保存的状态信息来实现从第一数据信道到第二数据信道的活动信道转换。耦合到每个功能单元的存储器单元可以包括分配给多个串行数据信道中的每一个的单独部分。可以从功能单元检索状态信息并存储在分配给第一数据信道的存储器单元的部分中。然后可以从分配给第二数据信道的存储器单元的部分检索状态信息，并将其存储在功能单元的存储元件内，从而完成状态“恢复”活动。

9. 发明授权

US06266715B1 Universal serial bus controller with a direct memory access mode 失效
标题翻译：通用串行总线控制器，具有直接存储器访问模式
公开(公告)号：US06266715B1
公开(公告)日：2001-07-24
申请号：US09088346
申请日：1998-06-01
申请人： Bruce A. Loyer , Daniel B. Reents , Allen B. Thor
发明人： Bruce A. Loyer , Daniel B. Reents , Allen B. Thor
IPC分类号： G06F1300
CPC分类号： G06F13/28
摘要： A universal serial bus (USB) device or host provides a universal serial bus (USB) controller with a direct memory access (DMA) mode. In a DMA mode, a universal serial bus (USB) transmit endpoint may be programmed for a direct memory access (DMA) transmit channel, or a universal serial bus (USB) receive endpoint may be programmed for a direct memory access (DMA) receive channel. For a USB device, a DMA transmit channel performs data transfer to a universal serial bus (USB) host, and a DMA receive channel handles data transfer from the USB host. For a USB host, a DMA transmit channel performs data transfer to the USB device, and a DMA receive channel handles data transfer from the USB device. A universal serial bus transmit protocol and a universal serial bus receive protocol for the DMA mode of the USB controller permit a maximum packet size of universal serial bus (USB) data to be programmed to a value greater than the physical size of a USB transmit or receive buffer of a USB transmit or receive endpoint. A USB controller with a DMA mode thus allows for a significant reduction in the buffer size of a USB transmit or receive buffer. A USB device having a controller with a DMA mode handles USB data as fast as the USB host can request USB data.
摘要翻译：通用串行总线（USB）设备或主机提供具有直接存储器访问（DMA）模式的通用串行总线（USB）控制器。在DMA模式下，通用串行总线（USB）传输端点可以被编程用于直接存储器访问（DMA）传输通道，或者通用串行总线（USB）接收端点可以被编程用于直接存储器访问（DMA）接收渠道。对于USB设备，DMA传输通道执行到通用串行总线（USB）主机的数据传输，DMA接收通道可以处理USB主机的数据传输。对于USB主机，DMA传输通道执行到USB设备的数据传输，DMA接收通道可以处理USB设备的数据传输。 USB控制器的DMA模式的通用串行总线传输协议和通用串行总线接收协议允许将通用串行总线（USB）数据的最大数据包大小编程为大于USB传输的物理尺寸接收USB发送或接收端点的缓冲区。因此，具有DMA模式的USB控制器可以显着降低USB发送或接收缓冲区的缓冲区大小。具有DMA模式的控制器的USB设备可以像USB主机请求USB数据那样快速处理USB数据。

10. 发明授权

US6067627A Core section having asynchronous partial reset 有权
标题翻译：核心部分具有异步部分重置
公开(公告)号：US6067627A
公开(公告)日：2000-05-23
申请号：US144319
申请日：1998-08-31
申请人： Daniel B. Reents
发明人： Daniel B. Reents
IPC分类号： G06F1/24 , G06F1/32
CPC分类号： G06F1/24
摘要： An integrated circuit is provided which comprises a core section, a plurality of input/output sections, and a pair of reset inputs. The first reset input is a master reset which initializes the entire integrated circuit. The second reset input is a partial reset. The partial reset initializes a portion of the integrated circuit while other portions remain in operation. The core section can include a plurality of subsystems such as a real time clock facility, a configuration RAM, and a DRAM memory controller. The real time clock facility and configuration RAM are not affected by the partial reset. Accordingly, the real time clock is maintained during partial reset, thereby maintaining accurate time/date and configuration data during partial reset. The DRAM controller is optionally reset based on a configuration bit stored in a configuration register in one of the plurality of subsystems. When not reset, the DRAM controller provides refresh to an array of DRAM memory cells, thereby maintaining the data stored within the DRAM memory cells. The integrated circuit can be configured into a personal information device, wherein a power conservation method can then be applied by resetting portions of the integrated circuit and powering down peripheral components and input/output driver sections associated with the reset portions. Additionally, discrete buffer devices are no longer required between the integrated circuit and the peripheral component.
摘要翻译：提供一种集成电路，其包括核心部分，多个输入/输出部分和一对复位输入。第一个复位输入是初始化整个集成电路的主复位。第二个复位输入是部分复位。部分复位初始化集成电路的一部分，而其他部分保持运行。核心部分可以包括多个子系统，例如实时时钟设施，配置RAM和DRAM存储器控制器。实时时钟设备和配置RAM不受部分重置的影响。因此，在部分复位期间保持实时时钟，从而在部分复位期间保持精确的时间/日期和配置数据。可选地，DRAM控制器基于存储在多个子系统之一中的配置寄存器中的配置位来重置。当不再复位时，DRAM控制器向DRAM存储器单元阵列提供刷新，从而保持存储在DRAM存储单元内的数据。集成电路可以被配置为个人信息设备，其中然后可以通过重置集成电路的部分并对与复位部分相关联的外围组件和输入/输出驱动器部分供电来施加功率节省方法。此外，集成电路和外围组件之间不再需要离散缓冲器件。

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