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1. 发明授权

US5596724A Input/output data port with a parallel and serial interface 失效
标题翻译：具有并行和串行接口的输入/输出数据端口
公开(公告)号：US5596724A
公开(公告)日：1997-01-21
申请号：US191948
申请日：1994-02-04
申请人： Jacqueline Mullins , Joseph W. Peterson , John Bartkowiak , Alan F. Hendrickson
发明人： Jacqueline Mullins , Joseph W. Peterson , John Bartkowiak , Alan F. Hendrickson
IPC分类号： G06F13/38 , G06F5/00 , H03M9/00
CPC分类号： H03M9/00
摘要： The present invention disclosed an input/output data port circuit which connects a parallel data bus with an input serial data bus and an output serial data bus. The input/output data port is selectively operable in either a linear mode or a buffered mode. The input/output port is comprised of an interface register that is connected to a parallel data bus, a serial input bus and a serial output bus; a temporary register that is serially connected to the interface register, an outbound register that is connected in parallel to the temporary register and serially connected to a serial bus; and an inbound register that is connected in parallel to the temporary register and serially connected to a serial, bus.
摘要翻译：本发明公开了一种将并行数据总线与输入串行数据总线和输出串行数据总线连接的输入/输出数据端口电路。输入/输出数据端口可选择性地以线性模式或缓冲模式工作。输入/输出端口包括连接到并行数据总线，串行输入总线和串行输出总线的接口寄存器; 串行连接到接口寄存器的临时寄存器，与临时寄存器并联并串行连接到串行总线的出站寄存器; 以及与临时寄存器并行连接并串行连接到串行总线的入站寄存器。

2. 发明授权

US5946353A Method and apparatus for external intermediate data processing 失效
标题翻译：用于外部中间数据处理的方法和装置
公开(公告)号：US5946353A
公开(公告)日：1999-08-31
申请号：US909383
申请日：1997-08-11
申请人： Jacqueline Mullins , Joseph W. Peterson , John Bartkowiak , Alan F. Hendrickson
发明人： Jacqueline Mullins , Joseph W. Peterson , John Bartkowiak , Alan F. Hendrickson
IPC分类号： H04B14/06 , H04M1/725
CPC分类号： H04M1/725
摘要： Disclosed is a system for selectively enabling intermediate data processing of digital signals external to an integrated circuit (IC). The system comprises a transcoder, a codec connected to the transcoder, and a data processor located externally to the IC. In response to a strobe signal, a programmable switch diverts digital signals between the transcoder and the codec to a data path from the IC to the external processor. The digital signals are formatted within the IC for processing by the external processor. The externally processed digital signals are returned to the IC via a data path from the external processor. The digital signals are then reformatted within the IC for further processing by the IC.
摘要翻译：公开了一种用于选择性地实现集成电路（IC）外部的数字信号的中间数据处理的系统。该系统包括代码转换器，连接到代码转换器的编解码器和位于IC外部的数据处理器。响应于选通信号，可编程开关将代码转换器和编解码器之间的数字信号转移到从IC到外部处理器的数据路径。数字信号在IC内格式化，由外部处理器进行处理。经外部处理的数字信号通过外部处理器的数据路径返回到IC。数字信号然后在IC内重新格式化，以便IC进一步处理。

3. 发明授权

US5657351A Method and apparatus for external intermediate data processing 失效
标题翻译：用于外部中间数据处理的方法和装置
公开(公告)号：US5657351A
公开(公告)日：1997-08-12
申请号：US668600
申请日：1996-06-19
申请人： Jacqueline Mullins , Joseph W. Peterson , John Bartkowiak , Alan F. Hendrickson
发明人： Jacqueline Mullins , Joseph W. Peterson , John Bartkowiak , Alan F. Hendrickson
IPC分类号： H04B14/06 , H04M1/725 , H04B14/08
CPC分类号： H04M1/725
摘要： Disclosed is a system for selectively enabling intermediate data processing of digital signals external to an integrated circuit (IC). The system comprises a transcoder, a codec connected to the transcoder, and a data processor located externally to the IC. In response to a strobe signal, a programmable switch diverts digital signals between the transcoder and the codec to a data path from the IC to the external processor. The digital signals are formatted within the IC for processing by the external processor. The externally processed digital signals are returned to the IC via a data path from the external processor. The digital signals are then reformatted within the IC for further processing by the IC.
摘要翻译：公开了一种用于选择性地实现集成电路（IC）外部的数字信号的中间数据处理的系统。该系统包括代码转换器，连接到代码转换器的编解码器和位于IC外部的数据处理器。响应于选通信号，可编程开关将代码转换器和编解码器之间的数字信号转换为从IC到外部处理器的数据路径。数字信号在IC内格式化，由外部处理器进行处理。经外部处理的数字信号通过外部处理器的数据路径返回到IC。数字信号然后在IC内重新格式化，以便IC进一步处理。

4. 发明授权

US5502689A Clock generator capable of shut-down mode and clock generation method 失效
标题翻译：具有关闭模式和时钟发生方式的时钟发生器
公开(公告)号：US5502689A
公开(公告)日：1996-03-26
申请号：US201077
申请日：1994-02-24
申请人： Joseph W. Peterson , Alan F. Hendrickson , Dale E. Gulick , Dean Grumlose
发明人： Joseph W. Peterson , Alan F. Hendrickson , Dale E. Gulick , Dean Grumlose
IPC分类号： H04B1/16 , G06F1/04 , G06F1/32 , H04B1/38 , H04B7/26 , G04F5/00 , G06F1/00
CPC分类号： G06F1/3287 , G06F1/3203 , Y02B60/1282 , Y02B60/32
摘要： A clock generator and interrupt bypass circuit for use in reducing the power consumption of the electrical system in which they are implemented. The clock generator provides module clock signals for sequencing modules within the same electrical system, and is capable of generating those module clock signals when in an active mode, and of not generating those module clock signals when in a stand-by mode. The clock generator is further capable of providing a delay of a predetermined length from a request to enter shut-down mode to actual entry into shut-down mode, allowing time to prepare the electrical system for shut-down mode. The interrupt bypass circuit provides a means of leaving shut-down mode in the event that the relevant interrupt requests have been masked.
摘要翻译：一个时钟发生器和中断旁路电路，用于降低实施电气系统的功耗。时钟发生器为同一电气系统中的排序模块提供模块时钟信号，并且能够在处于活动模式时产生那些模块时钟信号，并且在处于待机模式时不产生这些模块时钟信号。时钟发生器还能够提供从进入关闭模式的请求到实际进入关闭模式的预定长度的延迟，从而允许时间来准备用于关闭模式的电气系统。中断旁路电路提供了在相关中断请求已被屏蔽的情况下关闭模式的方法。

5. 发明授权

US5839061A Receiver quality measurement system for use in digital cordless telephones and like apparatus 失效
标题翻译：用于数字无绳电话和类似设备的接收机质量测量系统
公开(公告)号：US5839061A
公开(公告)日：1998-11-17
申请号：US531049
申请日：1995-09-20
申请人： Alan F. Hendrickson , Joseph W. Peterson
发明人： Alan F. Hendrickson , Joseph W. Peterson
IPC分类号： H04B1/10 , H04B7/08 , H04B17/00
CPC分类号： H04B1/1027 , H04B17/318 , H04B7/08
摘要： A communication circuit designed to be coupled to a radio receiver so as to receive a data signal and a receive signal strength indicator signal indicative of radio carrier strength therefrom, and further designed to be coupled to a controller, the communications circuit including a first, second, third, and fourth subcircuit. The first subcircuit receives the receive signal strength indicator from the receiver, determines radio carrier strength therefrom, and transfers the determined strength information to the controller. The second subcircuit receives the data signal from the receiver, determines if there are bit error within that signal, and transfers its determinations to the controller. The third subcircuit receives the data signal from the receiver, determines if there is jitter therein, and transfers its determinations to the controller. The fourth subcircuit is coupled to the second and third subcircuits to receive the output thereof, and is further coupled to the controller so as to receive output therefrom, the fourth subcircuit acting in response to the outputs to suppress signal noise.
摘要翻译：一种通信电路，被设计为耦合到无线电接收机，以便从其接收指示无线电载波强度的数据信号和接收信号强度指示符信号，并进一步设计为耦合到控制器，所述通信电路包括第一，第二，第三和第四分支电路。第一子电路从接收器接收接收信号强度指示符，从其确定无线电载波强度，并将确定的强度信息传送到控制器。第二分支电路接收来自接收机的数据信号，确定该信号内是否存在位错误，并将其确定传送给控制器。第三分支电路接收来自接收机的数据信号，确定其中是否存在抖动，并将其确定传送给控制器。第四子电路耦合到第二和第三子电路以接收其输出，并且还耦合到控制器，以便从其接收输出，第四子电路响应于输出而起作用以抑制信号噪声。

6. 发明授权

US5638405A Dual-mode baseband controller for radio-frequency interfaces relating to digital cordless telephones 失效
标题翻译：用于与数字无绳电话有关的射频接口的双模式基带控制器
公开(公告)号：US5638405A
公开(公告)日：1997-06-10
申请号：US192046
申请日：1994-02-04
申请人： Alan F. Hendrickson , Joseph W. Peterson
发明人： Alan F. Hendrickson , Joseph W. Peterson
IPC分类号： H04B1/40 , H04L27/12 , H04L27/20 , H04L27/26 , H04M1/00 , H04M1/725 , H04L27/04
CPC分类号： H04L27/12 , H04L27/2017 , H04M1/72502
摘要： A dual-mode baseband controller enables a single integrated circuit to support either In-Phase Quadrature (I-Q) or Non-Return to Zero (NRZ) radio-frequency transmitter architectures for use in second generation (CT2) cordless telephones. A radio frequency (RF) interface circuit controls output signals to support either the I-Q architecture or the NRZ architecture, depending on a MODE control bit received from a controlling integrated circuit. The RF interface circuit comprises an I-Q waveform generator, four multiplexers, two digital-to-analog converters, a buffer, interconnecting circuitry, and a timing controller operating under configurable software control.
摘要翻译：双模式基带控制器使单个集成电路能够支持用于第二代（CT2）无绳电话的同相正交（I-Q）或非归零（NRZ）射频发射机架构。根据从控制集成电路接收的MODE控制位，射频（RF）接口电路控制输出信号以支持I-Q架构或NRZ架构。 RF接口电路包括I-Q波形发生器，四个多路复用器，两个数模转换器，缓冲器，互连电路和在可配置的软件控制下操作的定时控制器。

7. 发明授权

US07024539B2 Resistor identification configuration circuitry and associated method 有权
公开(公告)号：US07024539B2
公开(公告)日：2006-04-04
申请号：US10190136
申请日：2002-07-03
申请人： David P. Bresemann , Alan F. Hendrickson , Robert C. Wagner
发明人： David P. Bresemann , Alan F. Hendrickson , Robert C. Wagner
IPC分类号： G06F15/00
CPC分类号： H01L23/544 , G05B2219/23336 , G06F9/4411 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： Programmable on-chip identification circuitry and associated method are disclosed that provide integrated circuits with the ability to select and report from multiple different vendor and system identification configurations. The integrated circuit device includes programmable circuitry that utilizes vendor identification, system identification, configuration or other device information provided or selected at least in part based upon selection information from a source external to the integrated circuit. The selection information may be provided through one or more externally generated digital and/or analog control signals that are then processed within the integrated circuit device to select, access and utilize desired identification information stored in an on-chip database. For example, one or more analog control signals can be generated using resistor circuits for which specific selectable resistor configurations map to particular information stored in a look-up table or other database structure within the integrated circuit. The analog control signals are converted to digital values within the integrated circuit, and these digital values are used to select device information from the on-chip database. Furthermore, the selected device information can be stored in on-chip device information registers. And the digital values themselves can be stored and used as identification, configuration or other device information.

8. 发明授权

US06510215B1 Caller ID data-reporting mechanism for electronic devices and associated methods 失效
标题翻译：用于电子设备和相关方法的来电显示数据报告机制
公开(公告)号：US06510215B1
公开(公告)日：2003-01-21
申请号：US09617757
申请日：2000-07-17
申请人： Alan F. Hendrickson
发明人： Alan F. Hendrickson
IPC分类号： H04M156
CPC分类号： H04M1/573
摘要： Caller ID (CID) data-reporting circuitry operates in conjunction with direct-access arrangement (DAA) circuitry or other circuitry that operates within the operational requirements of the Audio Codec '97 (AC-97) Component Specification. The CID data-reporting circuitry provides for the transfer of a data word from the DAA circuitry to a host computer or controller that operates within the AC-97 operational specifications. The CID data-reporting circuitry transfers the CID data in an asynchronous manner, i.e., at non-pre-determined intervals. Software running on the host computer or the controller may thus examine each data word or group of data words and take appropriate action, for example, process the data further or terminate the data transfer. A command interpreter begins the data transfer by initializing an address pointer used to facilitate retrieving the data from a CID random-access memory (RAM) and to make the data available to the host computer or controller through an output register.
摘要翻译：来电显示（CID）数据报告电路与直接访问布置（DAA）电路或在音频编解码器'97（AC-97）组件规范的操作要求中工作的其他电路一起操作。 CID数据报告电路提供数据字从DAA电路传输到在AC-97操作规范内运行的主机或控制器。 CID数据报告电路以异步方式，即以非预定间隔传送CID数据。因此，在主计算机或控制器上运行的软件可以检查每个数据字或数据字组，并采取适当的动作，例如进一步处理数据或终止数据传输。命令解释器通过初始化用于便于从CID随机存取存储器（RAM）检索数据的地址指针并通过输出寄存器使数据可用于主计算机或控制器来开始数据传输。

9. 发明授权

US06263013B1 Fast tracking of PN synchronization in a direct-sequence spread-spectrum digital communications system 有权
标题翻译：在直接序列扩频数字通信系统中快速跟踪PN同步
公开(公告)号：US06263013B1
公开(公告)日：2001-07-17
申请号：US09148537
申请日：1998-09-04
申请人： Alan F. Hendrickson
发明人： Alan F. Hendrickson
IPC分类号： H04B1500
CPC分类号： H04L1/24 , H04L7/0054 , H04L7/0334
摘要： In a direct sequence spread spectrum communication receiver, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment of the method, the receiver waits for detection of a SYNC field to confirm at least a coarse synchronization or the receiver's local PN sequence with the received PN sequence (in the received signal). The receiver then performs a fast tracking to finely synchronize the receiver's PN sequence with the received PN sequence, preferably for a fixed duration of time. One embodiment of a system for performing the synchronization with the fast tracking includes an input for receiving a received spread-spectrum data stream, an ML detection logic, a receiver PN clock, a despreading mixer that generates a narrowband signal from the spread-spectrum data stream, a testing logic that generates a PASS output if it identifies a SYNC field in the narrowband signal, and a fast-tracking logic. The fast-tracking logic temporarily advances and temporarily delays the receiver PN clock by a small shift and measures the resulting correlations between the receiver's PN sequence and the received PN sequence. If the advanced correlation is greater or less than the delayed correlation, then the fast-tracking logic accordingly makes a small adjustment to advance or delay the receiver PN clock. This temporary advancing, temporary delaying, and adjusting of the receiver PN clock is preferably repeated a fixed number of times.
摘要翻译：在直接序列扩频通信接收机中，用于恢复用于解扩接收信号的伪随机噪声（PN）序列的定时的系统和方法。在该方法的一个实施例中，接收机等待SYNC字段的检测，以至少确认具有接收到的PN序列（在接收到的信号中）的粗略同步或接收机的本地PN序列。然后，接收机执行快速跟踪以将接收机的PN序列与接收到的PN序列精细同步，优选地在固定的持续时间内。用于执行与快速跟踪同步的系统的一个实施例包括用于接收接收的扩频数据流的输入，ML检测逻辑，接收器PN时钟，从扩展频谱数据产生窄带信号的去扩频混频器流，测试逻辑，如果它识别窄带信号中的SYNC字段，则产生PASS输出，以及快速跟踪逻辑。快速跟踪逻辑临时前进并暂时将接收器PN时钟延迟一小段移位，并测量接收机的PN序列与接收到的PN序列之间产生的相关性。如果高级相关性大于或小于延迟相关，则快速跟踪逻辑相应地进行小的调整以提前或延迟接收器PN时钟。优选地，重复固定次数的临时提前，临时延迟和接收器PN时钟的调整。

10. 发明授权

US06212246B1 Symbol-quality evaluation in a digital communications receiver 失效
标题翻译：数字通信接收机中的符号质量评估
公开(公告)号：US06212246B1
公开(公告)日：2001-04-03
申请号：US09078225
申请日：1998-05-13
申请人： Alan F. Hendrickson
发明人： Alan F. Hendrickson
IPC分类号： H04L700
CPC分类号： H04L1/24 , H04L7/0054 , H04L7/0334
摘要： In a digital communications receiver, a system and method for evaluating the quality of received symbols and for initializing and adjusting a symbol clock. The invention presents a symbol quality detector that evaluates symbols which have been received by the receiver and detected in a matched filter. The received symbols are members of a constellation with elements that have purely I or purely Q components. The symbol-quality detector comprises inputs that receive the I and Q components of the symbols, and a logic block that generates the symbol-quality signal by constructing the quantity ||I|−|Q||. This quantity is a maximum when the detected symbols are aligned with the expected points in the symbol constellation, and decreases if the detected symbols are rotated away from these constellation points. The present invention further comprises a digital communications receiver that uses a symbol-quality detector to evaluate its symbol clock. Still further, the present invention contemplates a method for configuring the receiver with an IF delay value that indicates the timing of symbol transitions in a received signal processed by the receiver. In this embodiment of the invention, the receiver recovers a timing that has the same period as the symbol period, but which is out of phase with the received symbols. The method then determines an optimal delay value by which the symbol clock should be shifted from the recovered timing by using the symbol-quality signal to evaluate test delays and to successively refine them until the optimal delay value is found.
摘要翻译：在数字通信接收机中，用于评估接收符号的质量以及初始化和调整符号时钟的系统和方法。本发明提出了一种符号质量检测器，其评估接收机接收并在匹配滤波器中检测的符号。所接收的符号是具有纯I或纯Q分量的元素的星座的成员。符号质量检测器包括接收符号的I和Q分量的输入，以及通过构造量|| I | - | Q ||生成符号质量信号的逻辑块。当检测到的符号与符号星座中的预期点对准时，该量是最大值，如果检测到的符号从这些星座点旋转，则该量减小。本发明还包括使用符号质量检测器来评估其符号时钟的数字通信接收机。此外，本发明考虑了一种用于配置具有指示接收机处理的接收信号中的符号转换的定时的IF延迟值的接收机的方法。在本发明的这个实施例中，接收机恢复与符号周期具有相同周期但与接收到的符号不同步的定时。该方法然后通过使用符号质量信号来确定符号时钟应该从恢复的定时偏移的最佳延迟值，以评估测试延迟并连续细化它们直到找到最佳延迟值。

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