专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5448743A General I/O port interrupt mechanism 失效
标题翻译：一般I / O口中断机制
公开(公告)号：US5448743A
公开(公告)日：1995-09-05
申请号：US917497
申请日：1992-07-21
申请人： Dale E. Gulick , Joe W. Peterson , Munehiro Yoshikawa , Hiroshi Matsubara , Toshihiro Fujita , Kazushige Tsurumi
发明人： Dale E. Gulick , Joe W. Peterson , Munehiro Yoshikawa , Hiroshi Matsubara , Toshihiro Fujita , Kazushige Tsurumi
IPC分类号： G06F15/78 , G06F13/24 , G06F9/46
CPC分类号： G06F13/24
摘要： An I/O port interrupt mechanism includes a source register connected to the port for reporting sources of interrupts arising within the port, an interrupt mask register connected to the source register and operable to configure the I/O port for generation of interrupts, and an interrupt controller connected to the output of the source register and operable to hold off interrupts arising within the I/O port.
摘要翻译： I / O端口中断机制包括连接到端口的源寄存器，用于报告在端口内产生的中断源，中断屏蔽寄存器连接到源寄存器，并可用于配置I / O端口以产生中断，以及中断控制器连接到源寄存器的输出，可用于阻止I / O端口内产生的中断。

2. 发明授权

US5404459A Serial interface module and method in which the clock is only activated to send a predetermined number of data bits 失效
标题翻译：串行接口模块和方法，其中仅激活时钟以发送预定数量的数据位
公开(公告)号：US5404459A
公开(公告)日：1995-04-04
申请号：US918624
申请日：1992-07-21
申请人： Dale E. Gulick , Alan F. Hendrickson , Munehiro Yoshikawa , Hiroshi Matsubara , Kazushige Tsurumi
发明人： Dale E. Gulick , Alan F. Hendrickson , Munehiro Yoshikawa , Hiroshi Matsubara , Kazushige Tsurumi
IPC分类号： G06F15/78 , G06F1/04 , G06F13/42 , G06F1/32
CPC分类号： G06F13/423 , G06F1/04
摘要： A serial communication port structure for starting and stopping an internal clock. This internal clock is designed, in operation, to generate a clock output signal to be transmitted to a device external to the system in which the serial communication port is incorporated. By ANDing the clock output signal with a data output signal of predetermined length, the serial communication port can effectively control the passage of time as sensed by the external device.
摘要翻译：用于启动和停止内部时钟的串行通信端口结构。该内部时钟在工作时被设计为产生时钟输出信号，以将其发送到并入串行通信端口的系统外部的设备。通过将时钟输出信号与预定长度的数据输出信号进行AND操作，串行通信端口可以有效地控制由外部设备感测到的时间的流逝。

3. 发明授权

US5555287A Integrated circuit and cordless telephone using the integrated circuit 失效
标题翻译：集成电路和无绳电话采用集成电路
公开(公告)号：US5555287A
公开(公告)日：1996-09-10
申请号：US918627
申请日：1992-07-21
申请人： Dale E. Gulick , Joseph W. Peterson , James E. Bowles , John G. Bartkowiak , Munehiro Yoshikawa , Shin Saito , Hiroshi Matsubara
发明人： Dale E. Gulick , Joseph W. Peterson , James E. Bowles , John G. Bartkowiak , Munehiro Yoshikawa , Shin Saito , Hiroshi Matsubara
IPC分类号： H04Q7/32 , G06F11/00 , G06F11/26 , H04B1/40 , H04M1/00 , H04M1/725 , H04M1/73 , H04Q7/38
CPC分类号： H04M1/73 , H04B1/40 , H04M1/725 , G06F11/0757 , G06F11/261
摘要： An integrated circuit especially suitable for incorporation into the base and handset units of a cordless telephone integrates the speech, control channels, and microcontroller portions of a modem, and the man-machine interface functions of a cordless telephone. The integrated circuit includes one or more of a number of aspects including an in-circuit emulation mechanism, a simplified keypad reporting mechanism, advanced noise suppression mechanisms, a low power emergency mode mechanism, a low cost serial control bus, a port pin interrupt mechanism, advanced power saving mechanisms, spectral measurement test mode means, a novel shut down mechanism, and a pull-up disabling mechanism.
摘要翻译：特别适用于并入无绳电话的基座和手机单元的集成电路集成了调制解调器的语音，控制信道和微控制器部分，以及无绳电话的人机接口功能。集成电路包括多个方面中的一个或多个，包括在线仿真机制，简化的键盘报告机制，高级噪声抑制机制，低功率紧急模式机制，低成本串行控制总线，端口引脚中断机制先进的省电机制，光谱测量测试模式，新型关机机制和上拉禁用机制。

4. 发明授权

US5993057A Apparatus for detecting and averaging data in a digital data stream 失效
标题翻译：用于检测和平均数字数据流中的数据的装置
公开(公告)号：US5993057A
公开(公告)日：1999-11-30
申请号：US374191
申请日：1995-01-18
申请人： Dale E. Gulick , Satoru Maeda , Munehiro Yoshikawa , Manabu Oonishi
发明人： Dale E. Gulick , Satoru Maeda , Munehiro Yoshikawa , Manabu Oonishi
IPC分类号： H04L1/00 , H04L1/20 , G11B27/00
CPC分类号： H04L1/205
摘要： An apparatus for averaging pulses in a stream of pulses, which pulses are categorizable into at least two categories, includes structure for isolating the pulses into groupings of pulses, structure for counting the number of pulses of a particular category that occur within a grouping of pulses, and structure for generating an output signal when a predetermined number of pulses of a particular category occur within a grouping of pulses.
摘要翻译：用于对脉冲流中的脉冲进行平均的装置，这些脉冲可分为至少两个类别，包括用于将脉冲分离成脉冲组合的结构，用于对在脉冲组内发生的特定类别的脉冲数进行计数的结构以及当在一组脉冲内发生特定类别的预定数量的脉冲时产生输出信号的结构。

5. 发明授权

US5790833A Integrated circuit, having microprocessor and telephony peripheral circuitry, having capability of being placed in partial emulation mode 失效
标题翻译：具有微处理器和电话外围电路的集成电路具有被置于部分仿真模式的能力
公开(公告)号：US5790833A
公开(公告)日：1998-08-04
申请号：US843796
申请日：1997-04-21
申请人： Dale E. Gulick , Joseph William Peterson , Munehiro Yoshikawa
发明人： Dale E. Gulick , Joseph William Peterson , Munehiro Yoshikawa
IPC分类号： G06F15/78 , G06F11/36 , G06F11/00
CPC分类号： G06F11/3656 , G06F11/3652
摘要： An in-circuit emulation capability mode incorporated in an integrated circuit. The in-circuit emulation capability mode disables the microcontroller of the integrated circuit and allows use of an external in-circuit emulator device to test and debug the integrated circuit without the necessity of physically replacing the microcontroller with in-circuit emulator hardware. The in-circuit emulation capability mode is suitable for any integrated circuit, however, it has been found that integrated circuits incorporating an in-circuit emulation capability mode are especially suitable for incorporation into the base and handset units of a cordless telephone that integrates the speech, control channels, and microcontroller portions of a modem, and the man-machine interface functions of a cordless telephone.
摘要翻译：集成在集成电路中的在线仿真能力模式。在线仿真功能模式禁用集成电路的微控制器，并允许使用外部在线仿真器设备来测试和调试集成电路，而无需用在线仿真器硬件物理更换微控制器。在线仿真能力模式适用于任何集成电路，但是已经发现，集成了在线仿真能力模式的集成电路特别适用于将无线电话机的基座和手机单元整合到语音，控制信道和调制解调器的微控制器部分，以及无绳电话的人机接口功能。

6. 发明授权

US5420904A Signal averager 失效
标题翻译：信号平均机
公开(公告)号：US5420904A
公开(公告)日：1995-05-30
申请号：US918621
申请日：1992-07-21
申请人： Dale E. Gulick , Satoru Maeda , Munehiro Yoshikawa , Manabu Oonishi
发明人： Dale E. Gulick , Satoru Maeda , Munehiro Yoshikawa , Manabu Oonishi
IPC分类号： H04L1/00 , H04L1/20 , H03K21/38
CPC分类号： H04L1/205
摘要： An apparatus for averaging pulses in a stream of pulses, which pulses are categorizable into at least two categories, includes structure for isolating the pulses into groupings of pulses, structure for counting the number of pulses of a particular category that occur within a grouping of pulses, and structure for generating an output signal when a predetermined number of pulses of a particular category occur within a grouping of pulses.
摘要翻译：用于对脉冲流中的脉冲进行平均的装置，这些脉冲可分为至少两个类别，包括用于将脉冲分离成脉冲组合的结构，用于对在脉冲组内发生的特定类别的脉冲数进行计数的结构以及当在一组脉冲内发生特定类别的预定数量的脉冲时产生输出信号的结构。

7. 发明授权

US07603551B2 Initialization of a computer system including a secure execution mode-capable processor 有权
标题翻译：包括安全执行模式处理器的计算机系统的初始化
公开(公告)号：US07603551B2
公开(公告)日：2009-10-13
申请号：US10419121
申请日：2003-04-18
申请人： Kevin J. McGrath , Geoffrey S. Strongin , David S. Christie , William A. Hughes , Dale E. Gulick
发明人： Kevin J. McGrath , Geoffrey S. Strongin , David S. Christie , William A. Hughes , Dale E. Gulick
IPC分类号： G06F9/44 , H04L29/06
CPC分类号： G06F9/4403
摘要： The initialization of a computer system including a secure execution mode-capable processor includes storing a secure operating system code segment loader to a plurality of locations corresponding to a particular range of addresses within a system memory. The method also includes executing a security initialization instruction. Executing the security initialization instruction may cause several operations to be performed including transmitting a start transaction including a base address of the particular range of addresses. In addition, executing the security instruction may also cause another operation to be performed including retrieving the secure operating system code segment loader from the system memory and transmitting the secure operating system code segment loader for validation as a plurality of data transactions.
摘要翻译：包括具有安全执行模式能力的处理器的计算机系统的初始化包括将安全操作系统代码段加载器存储到对应于系统存储器内的特定地址范围的多个位置。该方法还包括执行安全初始化指令。执行安全初始化指令可能导致执行若干操作，包括发送包括特定地址范围的基地址的开始事务。此外，执行安全指令还可以引起执行另一操作，包括从系统存储器检索安全操作系统代码段加载器，并将安全操作系统代码段加载器发送为多个数据事务。

8. 发明授权

US07216362B1 Enhanced security and manageability using secure storage in a personal computer system 有权
标题翻译：在个人计算机系统中使用安全存储来增强安全性和可管理性
公开(公告)号：US07216362B1
公开(公告)日：2007-05-08
申请号：US09853395
申请日：2001-05-11
申请人： Geoffrey S. Strongin , Dale E. Gulick
发明人： Geoffrey S. Strongin , Dale E. Gulick
IPC分类号： G06F12/14 , G06F12/00 , G06F7/04 , G06F13/00
CPC分类号： G06F12/1441 , G06F7/582 , G06F12/1458 , G06F21/53 , G06F21/72
摘要： A method and system for enhanced security and manageability using secure storage. The system may include a crypto-processor and a memory coupled to receive memory transactions through the crypto-processor. The memory transactions are passed to the memory by the crypto-processor. The system may include a first processor, a second processor coupled to the first processor, and a storage device operably coupled to the first processor through the second processor. The second processor is configured to control access to the storage device. The method includes transmitting a request for a memory transaction for a storage location in the storage device and receiving the request for the memory transaction at the crypto-processor. The method also includes determining if the memory transaction is authorized for the storage location, and passing the request for the memory transaction to the storage device if the memory transaction is authorized for the storage location.
摘要翻译：一种使用安全存储来增强安全性和可管理性的方法和系统。该系统可以包括加密处理器和耦合以通过密码处理器接收存储器事务的存储器。存储器事务由加密处理器传递到存储器。该系统可以包括第一处理器，耦合到第一处理器的第二处理器，以及通过第二处理器可操作地耦合到第一处理器的存储设备。第二处理器被配置为控制对存储设备的访问。该方法包括向存储设备发送对存储位置的存储器事务的请求，并在密码处理器处接收对存储器事务的请求。该方法还包括确定存储器事务是否被授权用于存储位置，并且如果存储器事务被授权用于存储位置，则将存储器事务的请求传递到存储设备。

9. 发明授权

US07210009B2 Computer system employing a trusted execution environment including a memory controller configured to clear memory 有权
标题翻译：计算机系统采用可信执行环境，包括配置为清除存储器的存储器控制器
公开(公告)号：US07210009B2
公开(公告)日：2007-04-24
申请号：US10654734
申请日：2003-09-04
申请人： Dale E. Gulick , Geoffrey S. Strongin , William A. Hughes
发明人： Dale E. Gulick , Geoffrey S. Strongin , William A. Hughes
IPC分类号： G06F12/12 , G06F12/16
CPC分类号： G06F21/74 , G06F21/79 , G06F2221/2105 , G06F2221/2143
摘要： A computer system includes a processor which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includes a system memory configured to store data in a plurality of locations. The computer system also includes a memory controller which may selectively clear the data from a programmed range of the memory locations of the system memory when enabled in response to a reset of the processor.
摘要翻译：计算机系统包括可以通过执行安全初始化指令来初始化安全执行模式的处理器。此外，处理器可以通过执行安全操作系统代码段在安全执行模式下操作。计算机系统还包括被配置为在多个位置存储数据的系统存储器。计算机系统还包括存储器控制器，当响应于处理器的复位使能时，存储器控制器可以选择性地从系统存储器的存储器位置的编程范围中清除数据。

10. 发明授权

US07174467B1 Message based power management in a multi-processor system 有权
标题翻译：多处理器系统中基于消息的电源管理
公开(公告)号：US07174467B1
公开(公告)日：2007-02-06
申请号：US10185171
申请日：2002-06-28
申请人： Frank P. Helms , Dale E. Gulick , Larry D. Hewitt , William A. Hughes , Paul C. Miranda , Derrick R. Meyer , Scott E. Swanstrom , Scott A. White
发明人： Frank P. Helms , Dale E. Gulick , Larry D. Hewitt , William A. Hughes , Paul C. Miranda , Derrick R. Meyer , Scott E. Swanstrom , Scott A. White
IPC分类号： G06F1/26 , G06F1/28 , G06F1/32
CPC分类号： G06F1/324 , G06F1/3228 , G06F1/3296 , G06F9/30083 , Y02D10/126 , Y02D10/172
摘要： A message based power management approach is utilized to provide power management for a multi-processor system. A power management message is received at one processor of the multi-processor system over an input/output communication link that provides input/output access for the processors of the multi-processor system. The power management message includes a power management field encoding a power management state for processors of the multi-processor system. The processor that received the power management message over the input/output communication link sends a power management message to other processors in the multi-processor system over one or more inter-processor communication links encoding the power management state.
摘要翻译：利用基于消息的电源管理方法为多处理器系统提供电源管理。在多处理器系统的一个处理器上通过输入/输出通信链路接收功率管理消息，该输入/输出通信链路为多处理器系统的处理器提供输入/输出接入。电源管理消息包括对多处理器系统的处理器编码电源管理状态的电源管理字段。通过输入/输出通信链路接收电力管理消息的处理器通过编码电源管理状态的一个或多个处理器间通信链路向多处理器系统中的其他处理器发送电源管理消息。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式