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1. 发明授权

US06286095B1 Computer apparatus having special instructions to force ordered load and store operations 失效
标题翻译：具有强制有序加载和存储操作的特殊指令的计算机设备
公开(公告)号：US06286095B1
公开(公告)日：2001-09-04
申请号：US08533878
申请日：1995-09-26
申请人： Dale C. Morris , Barry J. Flahive , Michael L. Ziegler , Jerome C. Huck , Stephen G. Burger , Ruby B. L. Lee , Bernard L. Stumpf , Jeff Kurtze
发明人： Dale C. Morris , Barry J. Flahive , Michael L. Ziegler , Jerome C. Huck , Stephen G. Burger , Ruby B. L. Lee , Bernard L. Stumpf , Jeff Kurtze
IPC分类号： G06F1314
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/30087
摘要： A computer apparatus incorporating special instructions to force load and store operations to execute in program order. The present invention provides a new and novel store instruction that is suspended until all prior store instructions have been completed by an associated CPU. Also, a new load instruction is provided which blocks any subsequent load instructions from executing until this load instruction has been completed by an associated CPU. These instructions allow for high efficiency computer systems to be implemented which optimize instruction throughput by executing subsequent instructions while waiting for a prior instruction to complete.
摘要翻译：一种包含强制加载和存储操作的特殊指令的计算机设备，以程序顺序执行。本发明提供了一种新的和新颖的存储指令，直到所有先前存储指令已经被相关联的CPU完成为止。此外，提供了新的加载指令，其阻止任何后续的加载指令执行，直到该加载指令已由相关联的CPU完成。这些指令允许实现高效率的计算机系统，其通过在等待先前的指令完成的同时执行后续指令来优化指令吞吐量。

2. 发明授权

US6079012A Computer that selectively forces ordered execution of store and load operations between a CPU and a shared memory 失效
标题翻译：选择性地强制执行CPU和共享内存之间的存储和加载操作的计算机
公开(公告)号：US6079012A
公开(公告)日：2000-06-20
申请号：US968923
申请日：1997-11-06
申请人： Dale C. Morris , Bernard L. Stumpf , Barry J. Flahive , Jeffrey D. Kurtze , Stephen G. Burger , Ruby B. L. Lee , William R. Bryg
发明人： Dale C. Morris , Bernard L. Stumpf , Barry J. Flahive , Jeffrey D. Kurtze , Stephen G. Burger , Ruby B. L. Lee , William R. Bryg
IPC分类号： G06F15/16 , G06F9/38 , G06F9/46 , G06F9/52 , G06F15/177 , G06F15/163
CPC分类号： G06F9/52 , G06F9/30087 , G06F9/3834 , G06F9/522
摘要： A computer apparatus which detects a store or load operation into or from a shared memory page by a program that does not provide for synchronization when executed by a CPU that completes instructions out of program order. After the store or load is detected, the CPU explicitly orders operations into the shared memory page. Store operations are ordered such that no new store into the shared memory page is performed until all prior store operations into the shared memory page are complete. Also, load operations are ordered such that load operations from the shared memory page are performed in program order. This ordering is achieved by maintaining a process bit and a memory attribute bit associated with a shared memory page. When both bits are true, all load or store operations referencing the shared memory page are ordered.
摘要翻译：一种计算机装置，其通过程序执行存储或加载操作，所述程序在由程序顺序完成指令的CPU执行时不提供同步。检测到存储或加载后，CPU会将操作明确地命令到共享内存页面中。存储操作被排序，使得在共享存储器页面中的所有先前的存储操作完成之前，不执行在共享存储器页面中的新存储。此外，加载操作被排序，使得来自共享存储器页面的加载操作以程序顺序执行。该排序通过维护与共享存储器页相关联的进程位和存储器属性位来实现。当两个位都为真时，将对所有引用共享存储器页面的加载或存储操作进行排序。

3. 发明授权

US5278985A Software method for implementing dismissible instructions on a computer 失效
标题翻译：在计算机上实现可否允许的指令的软件方法
公开(公告)号：US5278985A
公开(公告)日：1994-01-11
申请号：US606711
申请日：1990-10-31
申请人： Daryl K. Odnert , Michael J. Mahon , Dale C. Morris , Jerome C. Huck , Ruby B. Lee , Stephen G. Burger , William R. Bryg , Vivek S. Pendharkar
发明人： Daryl K. Odnert , Michael J. Mahon , Dale C. Morris , Jerome C. Huck , Ruby B. Lee , Stephen G. Burger , William R. Bryg , Vivek S. Pendharkar
IPC分类号： G06F9/30 , G06F9/38 , G06F9/32
CPC分类号： G06F9/3865
摘要： A method for operating a digital computer in response to the occurrence of an exception is disclosed. The method provides for the examination both of the contents of a predetermined computer location and of the instruction code for the instruction causing the exception. The computer then utilizes the result of those examinations to determine the dismissibility of the exception. The computer transfers control to the next instruction after the instruction which caused the exception if that instruction is dismissible.
摘要翻译：公开了一种响应于异常发生而操作数字计算机的方法。该方法提供检查预定计算机位置的内容和引起异常的指令的指令代码。然后，计算机利用这些检查的结果来确定异常的可解除性。如果该指令被忽略，则计算机将控制转移到导致异常的指令之后的下一个指令。

4. 发明授权

US5928356A Method and apparatus for selectively controlling groups of registers 失效
标题翻译：用于选择性地控制寄存器组的方法和装置
公开(公告)号：US5928356A
公开(公告)日：1999-07-27
申请号：US947541
申请日：1997-10-11
申请人： Roger A. Golliver , Jerome C. Huck , Dale C. Morris
发明人： Roger A. Golliver , Jerome C. Huck , Dale C. Morris
IPC分类号： G06F9/30 , G06F9/318 , G06F9/46 , G06F9/312
CPC分类号： G06F9/30123 , G06F9/30076 , G06F9/30101 , G06F9/3013 , G06F9/462
摘要： A method and apparatus for controlling groups of registers includes a pluity of registers of the same type logically separated into a plurality of groups and a plurality of indicators corresponding to the plurality of groups of registers, each of the plurality of indicators identifying whether a corresponding group of registers has been modified by a task currently being executed by the processor. A control logic is also included, coupled to the plurality of registers, to selectively control the plurality of registers by group based at least in part on the plurality of indicators.
摘要翻译：用于控制寄存器组的方法和装置包括：逻辑上分成多个组的相同类型的多个寄存器和对应于多组寄存器的多个指示符，多个指示符中的每一个指示符标识相应组的寄存器已由当前由处理器执行的任务修改。还包括耦合到多个寄存器的控制逻辑，以至少部分地基于多个指示符按组选择性地控制多个寄存器。

5. 发明授权

US07103880B1 Floating-point data speculation across a procedure call using an advanced load address table 失效
标题翻译：使用高级加载地址表在整个过程调用中进行浮点数据推测
公开(公告)号：US07103880B1
公开(公告)日：2006-09-05
申请号：US10426505
申请日：2003-04-30
申请人： Dale C. Morris , Jerome C. Huck
发明人： Dale C. Morris , Jerome C. Huck
IPC分类号： G06F9/45 , G06F15/00
CPC分类号： G06F8/441
摘要： A method of converting an original code sequence to a modified code sequence where the original code sequence includes a procedure call that is prior to a load instruction that is configured to load a value into one of a first plurality of registers is provided. The method includes inserting an advanced load instruction associated with one of a second plurality of registers into the modified code sequence where the advanced load instruction is configured to cause the value to be loaded into the one of the first plurality of registers. The method also includes inserting the procedure call into the modified code sequence subsequent to the advanced load instruction and inserting a checking instruction associated with the one of the second plurality of registers into the modified code sequence subsequent to the procedure call.
摘要翻译：提供了将原始代码序列转换为修改的代码序列的方法，其中原始代码序列包括在被配置为将值加载到第一多个寄存器之一中的加载指令之前的过程调用。该方法包括将与第二多个寄存器中的一个相关联的高级加载指令插入到经修改的代码序列中，其中高级加载指令被配置为使得该值被加载到第一多个寄存器中的一个中。该方法还包括将过程调用插入到高级加载指令之后的修改代码序列中，并且将与第二多个寄存器中的一个寄存器相关联的检查指令插入到过程调用之后的修改代码序列中。

6. 发明授权

US06505296B2 Emulated branch effected by trampoline mechanism 失效
公开(公告)号：US06505296B2
公开(公告)日：2003-01-07
申请号：US09521160
申请日：2000-03-08
申请人： Dale C. Morris , Jonathan K. Ross , James O. Hays , Jerome C. Huck
发明人： Dale C. Morris , Jonathan K. Ross , James O. Hays , Jerome C. Huck
IPC分类号： G06F942
CPC分类号： G06F9/3834 , G06F8/445 , G06F9/3838 , G06F9/3842 , G06F9/3861 , G06F11/1407
摘要： A computer system includes a processor for executing a program and an interruption handler from a memory. The processor includes an instruction pointer indicating a memory location of a current executing instruction. The processor executes a trampoline check instruction in the program which tests a condition and if the condition is true, causes an interruption and supplies an address displacement. The interruption handler responds to the interruption and restarts execution of the program at a restart point indicating a memory location of a special handler in the program. The restart point is a sum of the address displacement and a value of the instruction pointer at the time of the interruption. If the condition is false, normal control flow of the program is continued.

7. 发明授权

US5724538A Computer memory address control apparatus utilizing hashed address tags in page tables which are compared to a combined address tag and index which are longer than the basic data width of the associated computer 失效
标题翻译：计算机存储器地址控制装置利用页表中的散列地址标签，其与组合的地址标签和索引进行比较，该地址标签和索引比相关计算机的基本数据宽度更长
公开(公告)号：US5724538A
公开(公告)日：1998-03-03
申请号：US607622
申请日：1996-02-27
申请人： Dale C. Morris , Jerome C. Huck , William R. Bryg
发明人： Dale C. Morris , Jerome C. Huck , William R. Bryg
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1018
摘要： The present invention relates to the design of computer systems incorporating virtual memory where a virtual page number is longer than the inherent basic data width of the designed computer system. Instead of storing an entire tag in page table entries, a reduced tag is stored. The reduced tag is sized to be no greater in length than the basic computer data width and therefore a single compare operation will ascertain whether there is a match between the reduced tag and the tag stored in a page table entry. To maintain uniqueness of the page table entries, any bits removed from the virtual address to form the reduced tag are used to form an index into the page table.
摘要翻译：本发明涉及包含虚拟存储器的计算机系统的设计，其中虚拟页码长于设计的计算机系统的固有基本数据宽度。代替在页表条目中存储整个标签，而不是存储缩小的标签。缩小标签的大小的长度不应大于基本计算机数据宽度，因此单个比较操作将确定缩小的标签与存储在页表条目中的标签之间是否存在匹配。为了保持页表项的唯一性，使用从虚拟地址中删除以形成缩减标记的任何位来形成页表中的索引。

8. 发明授权

US5915117A Computer architecture for the deferral of exceptions on speculative instructions 失效
标题翻译：计算机架构，用于推测投机说明上的例外
公开(公告)号：US5915117A
公开(公告)日：1999-06-22
申请号：US949295
申请日：1997-10-13
申请人： Jonathan K. Ross , Jack D. Mills , James O. Hays , Stephen G. Burger , Dale C. Morris , Carol L. Thompson , Rajiv Gupta , Stefan M. Freudenberger , Gary N. Hammond , Ralph M. Kling
发明人： Jonathan K. Ross , Jack D. Mills , James O. Hays , Stephen G. Burger , Dale C. Morris , Carol L. Thompson , Rajiv Gupta , Stefan M. Freudenberger , Gary N. Hammond , Ralph M. Kling
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F9/3842
摘要： The inventive system and method allows for software control of hardware drral of exceptions in speculative operations, and comprises three components. The first component is processor stored information which reflects the code generation strategy of applications and is used by hardware and the operating system to control exception deferral. The second component is processor stored information set by the operating system to specify to hardware which type of faults should be automatically deferred. The third component is further processor stored information which indicates to the hardware to defer certain exception causing aspects of the speculative operation, while performing other non excepting aspects of the speculative operation. The stored information is set after the operating system exception handler has unsuccessfully attempted fault resolution.
摘要翻译：本发明的系统和方法允许软件控制在推测操作中硬件推迟异常，并且包括三个组件。第一个组件是反映应用程序的代码生成策略的处理器存储信息，由硬件和操作系统用来控制异常延期。第二个组件是由操作系统设置的处理器存储信息，用于指定硬件哪种类型的故障应该自动延迟。第三组件是进一步处理器存储的信息，其指示硬件推迟导致投机操作方面的某些异常，同时执行投机操作的其他非例外方面。存储的信息在操作系统异常处理程序未成功尝试故障解决之后进行设置。

9. 发明授权

US08505020B2 Computer workload migration using processor pooling 有权
标题翻译：使用处理器池的计算机工作负载迁移
公开(公告)号：US08505020B2
公开(公告)日：2013-08-06
申请号：US12870835
申请日：2010-08-29
申请人： Christophe de Dinechin , Dale C. Morris , Patrick Knebel , Russ W. Herrell
发明人： Christophe de Dinechin , Dale C. Morris , Patrick Knebel , Russ W. Herrell
IPC分类号： G06F9/46 , G06F15/173 , G06F1/00 , G06F11/00
CPC分类号： G06F9/5088
摘要： An event calling for a migration of a workload from a source processor set of processing units to a target processor set of processing units is detected. Processes of the workload are allocated to a second processor set of processing units so that some workload processes are executed on the source processor set and some workload processes are executed on a second processor set of processor units. Then, some workload processes are allocated to the second processor set so that no workload process is executing on the source processor set and at least some of said processes are executing on the second process set. The second processor set can be the target processor set or an intermediate processor set from which the workload is migrated to the target processor set.
摘要翻译：检测到要求将工作负载从源处理器集合处理单元迁移到处理单元集合的事件。工作负载的处理被分配给处理单元的第二处理器集合，使得在源处理器集上执行一些工作负载过程，并且在第二处理器单元集合上执行一些工作负载过程。然后，一些工作负载过程被分配给第二处理器集，使得在源处理器集上不执行工作负载过程，并且至少一些所述进程在第二进程集上执行。第二处理器集合可以是目标处理器集合或中间处理器集合，工作负载从该集中迁移到目标处理器集合。

10. 发明授权

US08219996B1 Computer processor with fairness monitor 有权
标题翻译：具有公平监视器的计算机处理器
公开(公告)号：US08219996B1
公开(公告)日：2012-07-10
申请号：US11746067
申请日：2007-05-09
申请人： Dale C. Morris
发明人： Dale C. Morris
IPC分类号： G06F9/46 , G06F15/173 , G06F9/30 , G06F13/00
CPC分类号： G06F9/4881
摘要： A computer processor includes a fairness monitor for monitoring allocations of a processor resource to requestors. If unfairness is determined, a resource allocator is biased to offset said unfairness.
摘要翻译：计算机处理器包括用于监视对请求者的处理器资源的分配的公平监视器。如果确定不公平，则资源分配者有偏见以抵消所述不公平性。

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